[FFmpeg-devel] [PATCH] ac3dsp: RISC-V V float_to_fixed24
Rémi Denis-Courmont
remi at remlab.net
Wed Nov 22 16:51:41 EET 2023
Le 22 novembre 2023 16:30:44 GMT+02:00, flow gg <hlefthleft at gmail.com> a écrit :
>> How did you test it?
>
>I wrote a test, but it was a bit rough, so I want to modify it before
>submitting. I've added it to this reply.
>
>> This does not seem according to the C ABI. AFAIK `unsigned` is
>sign-extended.
>
>I'm a bit confused... because this passed in the tests I wrote in qemu.
>Maybe there's a problem with my test?
You probably didn't test sizes between 2^31 and 2^32-1. This might not even be feasible in QEMU.
Ideally the prototype would use size_t, then the problem wouldn't exist.
>
>> ALU right before dependent conditional branch should be avoided.
>
>Should the sub be moved forward? I've modified it.
>
>> SHxADD can be used advantageously.
>
>Okay, I've made the modification
>
>Rémi Denis-Courmont <remi at remlab.net> 于2023年11月22日周三 21:41写道:
>
>> Hi,
>>
>> How did you test it? As per
>> http://ffmpeg.org/pipermail/ffmpeg-devel/2023-June/310720.html we still
>> don't have a FATE instance set up with the RISC-V Vector extension. The
>> only testing consists of my manual runs of checkasm on a K230 board. (We
>> *do* have Zba and Zbb now though, hence the existing extract_exponents()).
>>
>> Also:
>> - This does not seem according to the C ABI. AFAIK `unsigned` is
>> sign-extended.
>> - ALU right before dependent conditional branch should be avoided.
>> - SHxADD can be used advantageously.
>>
>>
>> Le 22 novembre 2023 14:00:07 GMT+02:00, flow gg <hlefthleft at gmail.com> a
>> écrit :
>> >c910
>> > float_to_fixed24_c: 208.2
>> > float_to_fixed24_rvv_f32: 71.5
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