Update of /cvsroot/mplayer/main/vidix/drivers In directory mail:/var/tmp.root/cvs-serv17833 Modified Files: nvidia_vid.c Log Message: Sometimes (especially with big images) reading pitch 0 from card's register returns 0 (probably due to full card's FIFO), which leads to SIGFPE later. Fixed (or workarounded) by rereading pitch0, until it's not zero. Index: nvidia_vid.c =================================================================== RCS file: /cvsroot/mplayer/main/vidix/drivers/nvidia_vid.c,v retrieving revision 1.7 retrieving revision 1.8 diff -u -r1.7 -r1.8 --- nvidia_vid.c 28 Sep 2003 04:52:38 -0000 1.7 +++ nvidia_vid.c 1 Oct 2003 21:03:00 -0000 1.8 @@ -419,6 +419,7 @@ /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/ info->chip.lock (&info->chip, 0); + do { switch (info->chip.arch) { case NV_ARCH_03: pitch0 = info->chip.PGRAPH[0x00000650/4]; @@ -430,6 +431,9 @@ pitch0 = info->chip.PGRAPH[0x00000670/4]; break; } + if (pitch0 == 0) + printf("[nvidia_vid]: pitch0 = 0!!! Rereading\n"); + } while (pitch0 == 0); VID_WR08(info->chip.PCIO, 0x03D4, 0x28); bpp = VID_RD08(info->chip.PCIO,0x03D5); if(bpp==3)bpp = 4; //fixme do nvidia cards support 24bpp? @@ -438,7 +442,7 @@ if(!bpp)printf("[nvidia_vid] error invalid bpp\n"); else { -// printf("[nvidia_vid] video mode: %ux%u@%u\n",screen_x = pitch0/bpp,(pitch0/bpp*3)/4,info->depth); +// printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x = pitch0/bpp,(pitch0/bpp*3)/4,info->depth); info->screen_x = pitch0/bpp; } @@ -673,6 +677,7 @@ { uint32_t bpp=0,pitch0=0; info->chip.lock (&info->chip, 0); + do { switch (info->chip.arch) { case NV_ARCH_03: pitch0 = info->chip.PGRAPH[0x00000650/4]; @@ -684,6 +689,9 @@ pitch0 = info->chip.PGRAPH[0x00000670/4]; break; } + if (pitch0 == 0) + printf("[nvidia_vid]: pitch0 = 0!!! Rereading\n"); + } while (pitch0 == 0); VID_WR08(info->chip.PCIO, 0x03D4, 0x28); bpp = VID_RD08(info->chip.PCIO,0x03D5); if(bpp==3)bpp = 4; //fixme do nvidia cards support 24bpp?