Update of /cvsroot/mplayer/main/vidix/drivers
In directory mail:/var/tmp.root/cvs-serv17616/drivers
Modified Files:
Makefile mach64.h mach64_vid.c radeon.h radeon_vid.c
Added Files:
pm3_regs.h pm3_vid.c
Log Message:
rage128/radeon fixes, mach64 mess^H^H^H^Hcleanup, pm3 driver.
sync with mplayerxp
--- NEW FILE ---
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/glint/pm3_regs.h,v 1.9 2001/11/20 00:09:15 alanh Exp $ */
/*
* glint register file
*
* Copyright by Sven Luther
* Authors: Sven Luther, <luther(a)dpt-info.u-strasbg.fr>
* Thomas Witzel, <twitzel(a)nmr.mgh.harvard.edu>
*
* this work is sponsored by Appian Graphics.
*
*/
#ifndef _PM3_REG_H_
#define _PM3_REG_H_
/**********************************************
* GLINT Permedia3 Control Status registers *
***********************************************/
[...1074 lines suppressed...]
#define RAMDAC_SET_INDEX(index) \
{ \
SLOW_WRITE_REG (PM3RD_IndexHigh,(index>>8)&0xff); \
SLOW_WRITE_REG (PM3RD_IndexLow,index&0xff); \
}
#define RAMDAC_SET_REG(index, data) \
{ \
RAMDAC_SET_INDEX(index); \
SLOW_WRITE_REG(PM3RD_IndexedData, data); \
}
#define RAMDAC_GET_REG(index, temp) \
{ \
RAMDAC_SET_INDEX(index); \
temp = READ_REG(PM3RD_IndexedData); \
}
#endif
#endif /* _PM3_REG_H_ */
--- NEW FILE ---
/**
Driver for 3DLabs GLINT R3 and Permedia3 chips.
Copyright (C) 2002 Måns Rullgård
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
**/
#include <errno.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <unistd.h>
#include "../vidix.h"
#include "../fourcc.h"
#include "../../libdha/libdha.h"
#include "../../libdha/pci_ids.h"
#include "../../libdha/pci_names.h"
#include "../../config.h"
#include "pm3_regs.h"
#if 0
#define TRACE_ENTER() fprintf(stderr, "%s: enter\n", __FUNCTION__)
#define TRACE_EXIT() fprintf(stderr, "%s: exit\n", __FUNCTION__)
#else
#define TRACE_ENTER()
#define TRACE_EXIT()
#endif
pciinfo_t pci_info;
void *pm3_reg_base;
void *pm3_mem;
static vidix_capability_t pm3_cap =
{
"3DLabs GLINT R3/Permedia3 driver",
"Måns Rullgård <mru(a)users.sf.net>",
TYPE_OUTPUT,
{ 0, 0, 0, 0 },
2048,
2048,
4,
4,
-1,
FLAG_UPSCALER|FLAG_DOWNSCALER,
VENDOR_3DLABS,
-1,
{ 0, 0, 0, 0 }
};
unsigned int vixGetVersion(void)
{
return(VIDIX_VERSION);
}
static unsigned short pm3_card_ids[] =
{
DEVICE_3DLABS_GLINT_R3
};
static int find_chip(unsigned chip_id)
{
unsigned i;
for(i = 0;i < sizeof(pm3_card_ids)/sizeof(unsigned short);i++)
{
if(chip_id == pm3_card_ids[i]) return i;
}
return -1;
}
int vixProbe(int verbose, int force)
{
pciinfo_t lst[MAX_PCI_DEVICES];
unsigned i,num_pci;
int err;
err = pci_scan(lst,&num_pci);
if(err)
{
printf("[pm3] Error occured during pci scan: %s\n",strerror(err));
return err;
}
else
{
err = ENXIO;
for(i=0; i < num_pci; i++)
{
if(lst[i].vendor == VENDOR_3DLABS)
{
int idx;
const char *dname;
idx = find_chip(lst[i].device);
if(idx == -1)
continue;
dname = pci_device_name(VENDOR_3DLABS, lst[i].device);
dname = dname ? dname : "Unknown chip";
printf("[pm3] Found chip: %s\n", dname);
pm3_cap.device_id = lst[i].device;
err = 0;
memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
break;
}
}
}
if(err && verbose) printf("[pm3] Can't find chip\n");
return err;
}
#define PRINT_REG(reg) \
{ \
long _foo = READ_REG(reg); \
printf("[pm3] " #reg " (%x) = %#lx (%li)\n", reg, _foo, _foo); \
}
int vixInit(void)
{
pm3_reg_base = map_phys_mem(pci_info.base0, 0x20000);
pm3_mem = map_phys_mem(pci_info.base2, 0x2000000);
return 0;
}
void vixDestroy(void)
{
unmap_phys_mem(pm3_reg_base, 0x20000);
unmap_phys_mem(pm3_mem, 0x2000000);
}
int vixGetCapability(vidix_capability_t *to)
{
memcpy(to, &pm3_cap, sizeof(vidix_capability_t));
return 0;
}
static int is_supported_fourcc(uint32_t fourcc)
{
switch(fourcc){
case IMGFMT_YUY2:
case IMGFMT_UYVY:
return 1;
default:
return 0;
}
}
int vixQueryFourcc(vidix_fourcc_t *to)
{
if(is_supported_fourcc(to->fourcc))
{
to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP |
VID_DEPTH_4BPP | VID_DEPTH_8BPP |
VID_DEPTH_12BPP| VID_DEPTH_15BPP|
VID_DEPTH_16BPP| VID_DEPTH_24BPP|
VID_DEPTH_32BPP;
to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
return 0;
}
else to->depth = to->flags = 0;
return ENOSYS;
}
#define FORMAT_RGB8888 PM3VideoOverlayMode_COLORFORMAT_RGB8888
#define FORMAT_RGB4444 PM3VideoOverlayMode_COLORFORMAT_RGB4444
#define FORMAT_RGB5551 PM3VideoOverlayMode_COLORFORMAT_RGB5551
#define FORMAT_RGB565 PM3VideoOverlayMode_COLORFORMAT_RGB565
#define FORMAT_RGB332 PM3VideoOverlayMode_COLORFORMAT_RGB332
#define FORMAT_BGR8888 PM3VideoOverlayMode_COLORFORMAT_BGR8888
#define FORMAT_BGR4444 PM3VideoOverlayMode_COLORFORMAT_BGR4444
#define FORMAT_BGR5551 PM3VideoOverlayMode_COLORFORMAT_BGR5551
#define FORMAT_BGR565 PM3VideoOverlayMode_COLORFORMAT_BGR565
#define FORMAT_BGR332 PM3VideoOverlayMode_COLORFORMAT_BGR332
#define FORMAT_CI8 PM3VideoOverlayMode_COLORFORMAT_CI8
#define FORMAT_VUY444 PM3VideoOverlayMode_COLORFORMAT_VUY444
#define FORMAT_YUV444 PM3VideoOverlayMode_COLORFORMAT_YUV444
#define FORMAT_VUY422 PM3VideoOverlayMode_COLORFORMAT_VUY422
#define FORMAT_YUV422 PM3VideoOverlayMode_COLORFORMAT_YUV422
/* Notice, have to check that we dont overflow the deltas here ... */
static void
compute_scale_factor(
short* src_w, short* dst_w,
unsigned int* shrink_delta, unsigned int* zoom_delta)
{
/* NOTE: If we don't return reasonable values here then the video
* unit can potential shut off and won't display an image until re-enabled.
* Seems as though the zoom_delta is o.k, and I've not had the problem.
* The 'shrink_delta' is prone to this the most - FIXME ! */
if (*src_w >= *dst_w) {
*src_w &= ~0x3;
*dst_w &= ~0x3;
*shrink_delta = (((*src_w << 16) / *dst_w) + 0x0f) & 0x0ffffff0;
*zoom_delta = 1<<16;
if ( ((*shrink_delta * *dst_w) >> 16) & 0x03 )
*shrink_delta += 0x10;
} else {
*src_w &= ~0x3;
*dst_w &= ~0x3;
*zoom_delta = (((*src_w << 16) / *dst_w) + 0x0f) & 0x0001fff0;
*shrink_delta = 1<<16;
if ( ((*zoom_delta * *dst_w) >> 16) & 0x03 )
*zoom_delta += 0x10;
}
}
static int frames[VID_PLAY_MAXFRAMES];
static long overlay_mode, overlay_control;
int vixConfigPlayback(vidix_playback_t *info)
{
int shrink, zoom;
short src_w, drw_w;
short src_h, drw_h;
long base0;
int pitch;
int format;
unsigned int i;
TRACE_ENTER();
if(!is_supported_fourcc(info->fourcc))
return -1;
switch(info->fourcc){
case IMGFMT_YUY2:
format = FORMAT_YUV422;
break;
case IMGFMT_UYVY:
format = FORMAT_VUY422;
break;
default:
return -1;
}
src_w = info->src.w;
src_h = info->src.h;
drw_w = info->dest.w;
drw_h = info->dest.h;
pitch = src_w;
/* Assume we have 16 MB to play with */
info->num_frames = 0x1000000 / (pitch * src_h * 2);
if(info->num_frames > VID_PLAY_MAXFRAMES)
info->num_frames = VID_PLAY_MAXFRAMES;
/* Start at 16 MB. Let's hope it's not in use. */
base0 = 0x1000000;
info->dga_addr = pm3_mem + base0;
info->dest.pitch.y = 2;
info->dest.pitch.u = 0;
info->dest.pitch.v = 0;
info->offset.y = 0;
info->offset.v = 0;
info->offset.u = 0;
info->frame_size = pitch * src_h * 2;
for(i = 0; i < info->num_frames; i++){
info->offsets[i] = info->frame_size * i;
frames[i] = (base0 + info->offsets[i]) >> 1;
}
compute_scale_factor(&src_w, &drw_w, &shrink, &zoom);
WRITE_REG(PM3VideoOverlayBase0, base0 >> 1);
WRITE_REG(PM3VideoOverlayStride, PM3VideoOverlayStride_STRIDE(pitch));
WRITE_REG(PM3VideoOverlayWidth, PM3VideoOverlayWidth_WIDTH(src_w));
WRITE_REG(PM3VideoOverlayHeight, PM3VideoOverlayHeight_HEIGHT(src_h));
WRITE_REG(PM3VideoOverlayOrigin, 0);
/* Scale the source to the destinationsize */
if (src_h == drw_h) {
WRITE_REG(PM3VideoOverlayYDelta, PM3VideoOverlayYDelta_NONE);
} else {
WRITE_REG(PM3VideoOverlayYDelta,
PM3VideoOverlayYDelta_DELTA(src_h, drw_h));
}
if (src_w == drw_w) {
WRITE_REG(PM3VideoOverlayShrinkXDelta, 1<<16);
WRITE_REG(PM3VideoOverlayZoomXDelta, 1<<16);
} else {
WRITE_REG(PM3VideoOverlayShrinkXDelta, shrink);
WRITE_REG(PM3VideoOverlayZoomXDelta, zoom);
}
WRITE_REG(PM3VideoOverlayIndex, 0);
/* Now set the ramdac video overlay region and mode */
RAMDAC_SET_REG(PM3RD_VideoOverlayXStartLow, (info->dest.x & 0xff));
RAMDAC_SET_REG(PM3RD_VideoOverlayXStartHigh, (info->dest.x & 0xf00)>>8);
RAMDAC_SET_REG(PM3RD_VideoOverlayXEndLow, (info->dest.x+drw_w) & 0xff);
RAMDAC_SET_REG(PM3RD_VideoOverlayXEndHigh,
((info->dest.x+drw_w) & 0xf00)>>8);
RAMDAC_SET_REG(PM3RD_VideoOverlayYStartLow, (info->dest.y & 0xff));
RAMDAC_SET_REG(PM3RD_VideoOverlayYStartHigh, (info->dest.y & 0xf00)>>8);
RAMDAC_SET_REG(PM3RD_VideoOverlayYEndLow, (info->dest.y+drw_h) & 0xff);
RAMDAC_SET_REG(PM3RD_VideoOverlayYEndHigh,
((info->dest.y+drw_h) & 0xf00)>>8);
RAMDAC_SET_REG(PM3RD_VideoOverlayKeyR, 0xff);
RAMDAC_SET_REG(PM3RD_VideoOverlayKeyG, 0x00);
RAMDAC_SET_REG(PM3RD_VideoOverlayKeyB, 0xff);
overlay_mode =
1 << 5 |
format |
PM3VideoOverlayMode_FILTER_FULL |
PM3VideoOverlayMode_BUFFERSYNC_MANUAL |
PM3VideoOverlayMode_FLIP_VIDEO;
overlay_control =
PM3RD_VideoOverlayControl_KEY_COLOR |
PM3RD_VideoOverlayControl_MODE_MAINKEY |
PM3RD_VideoOverlayControl_DIRECTCOLOR_ENABLED;
TRACE_EXIT();
return 0;
}
int vixPlaybackOn(void)
{
TRACE_ENTER();
WRITE_REG(PM3VideoOverlayMode,
overlay_mode | PM3VideoOverlayMode_ENABLE);
RAMDAC_SET_REG(PM3RD_VideoOverlayControl,
overlay_control | PM3RD_VideoOverlayControl_ENABLE);
WRITE_REG(PM3VideoOverlayUpdate,
PM3VideoOverlayUpdate_ENABLE);
TRACE_EXIT();
return 0;
}
int vixPlaybackOff(void)
{
RAMDAC_SET_REG(PM3RD_VideoOverlayControl,
PM3RD_VideoOverlayControl_DISABLE);
WRITE_REG(PM3VideoOverlayMode,
PM3VideoOverlayMode_DISABLE);
RAMDAC_SET_REG(PM3RD_VideoOverlayKeyR, 0x01);
RAMDAC_SET_REG(PM3RD_VideoOverlayKeyG, 0x01);
RAMDAC_SET_REG(PM3RD_VideoOverlayKeyB, 0xfe);
return 0;
}
int vixPlaybackFrameSelect(unsigned int frame)
{
WRITE_REG(PM3VideoOverlayBase0, frames[frame]);
return 0;
}
Index: Makefile
===================================================================
RCS file: /cvsroot/mplayer/main/vidix/drivers/Makefile,v
retrieving revision 1.9
retrieving revision 1.10
diff -u -r1.9 -r1.10
--- Makefile 24 Apr 2002 19:58:33 -0000 1.9
+++ Makefile 31 May 2002 23:17:43 -0000 1.10
@@ -17,6 +17,12 @@
RAGE128_LIBS=-L../../libdha -ldha
RAGE128_CFLAGS=$(OPTFLAGS) -fPIC -I. -I.. -Wall -W -DRAGE128
+PM3_VID=pm3_vid.so
+PM3_SRCS=pm3_vid.c
+PM3_OBJS=pm3_vid.o
+PM3_LIBS=-L../../libdha -ldha
+PM3_CFLAGS=$(OPTFLAGS) -fPIC -I. -I.. -Wall -W
+
MACH64_VID=mach64_vid.so
MACH64_SRCS=mach64_vid.c
MACH64_OBJS=mach64_vid.o
@@ -47,13 +53,19 @@
MGA_CRTC2_LIBS=-L../../libdha -ldha -lm
MGA_CRTC2_CFLAGS=$(OPTFLAGS) -fPIC -I. -I.. -Wall -W -DCRTC2
-all: $(RADEON_VID) $(RAGE128_VID) $(MACH64_VID) $(NVIDIA_VID) $(GENFB_VID) $(MGA_VID) $(MGA_CRTC2_VID)
+all: $(RADEON_VID) $(RAGE128_VID) $(MACH64_VID) $(NVIDIA_VID) $(GENFB_VID) $(MGA_VID) $(MGA_CRTC2_VID) $(PM3_VID)
.SUFFIXES: .c .o
# .PHONY: all clean
+$(PM3_OBJS): $(PM3_SRCS)
+ $(CC) -c $(PM3_CFLAGS) -o $@ $<
+
+$(PM3_VID): $(PM3_OBJS)
+ $(LD) $(PM3_LIBS) -shared -soname $(PM3_VID) -o $(PM3_VID) $(PM3_OBJS)
+
$(RADEON_OBJS): $(RADEON_SRCS)
$(CC) -c $(RADEON_CFLAGS) -o $@ $<
@@ -105,11 +117,15 @@
dep: depend
depend:
- echo "depend not supported"
+# do nothing here
install:
mkdir -p $(BINDIR)
install -m 755 -s -p *.so $(BINDIR)
+uninstall:
+ rm -f $(BINDIR)/*.so
+ rmdir -p --ignore-fail-on-non-empty $(BINDIR)
+
#
# include dependency files if they exist
#
Index: mach64.h
===================================================================
RCS file: /cvsroot/mplayer/main/vidix/drivers/mach64.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -r1.3 -r1.4
--- mach64.h 25 Feb 2002 19:26:34 -0000 1.3
+++ mach64.h 31 May 2002 23:17:43 -0000 1.4
@@ -845,18 +845,19 @@
/* ? 0x80000000ul */
#define TV_OUT_DATA BlockIOTag(0x27u) /* LTPro */
#define BUS_CNTL IOPortTag(0x13u, 0x28u)
-#define BUS_WS 0x0000000ful
-#define BUS_DBL_RESYNC 0x00000001ul /* VTB/GTB/LT */
-#define BUS_MSTR_RESET 0x00000002ul /* VTB/GTB/LT */
-#define BUS_FLUSH_BUF 0x00000004ul /* VTB/GTB/LT */
-#define BUS_STOP_REQ_DIS 0x00000008ul /* VTB/GTB/LT */
-#define BUS_ROM_WS 0x000000f0ul
-#define BUS_APER_REG_DIS 0x00000010ul /* VTB/GTB/LT */
-#define BUS_EXTRA_PIPE_DIS 0x00000020ul /* VTB/GTB/LT */
-#define BUS_MASTER_DIS 0x00000040ul /* VTB/GTB/LT */
-#define BUS_ROM_WRT_EN 0x00000080ul /* GTPro */
-#define BUS_ROM_PAGE 0x00000f00ul
-#define BUS_MINOR_REV_ID 0x00000700ul /* LTPro */
+# define BUS_WS 0x0000000ful
+# define BUS_DBL_RESYNC 0x00000001ul /* VTB/GTB/LT */
+# define BUS_MSTR_RESET 0x00000002ul /* VTB/GTB/LT */
+# define BUS_FLUSH_BUF 0x00000004ul /* VTB/GTB/LT */
+# define BUS_STOP_REQ_DIS 0x00000008ul /* VTB/GTB/LT */
+# define BUS_ROM_WS 0x000000f0ul
+# define BUS_APER_REG_DIS 0x00000010ul /* VTB/GTB/LT */
+# define BUS_EXTRA_PIPE_DIS 0x00000020ul /* VTB/GTB/LT */
+# define BUS_MASTER_DIS 0x00000040ul /* VTB/GTB/LT */
+# define BUS_ROM_WRT_EN 0x00000080ul /* GTPro */
+# define BUS_ROM_PAGE 0x00000f00ul
+# define BUS_MINOR_REV_ID 0x00000700ul /* LTPro */
+# define BUS_EXT_REG_EN 0x08000000ul
/* First silicom - Prototype (A11) 0x00000000ul */
/* Metal mask spin (A12 & A13) 0x00000100ul */
/* All layer spin (A21) 0x00000200ul */
@@ -1283,20 +1284,24 @@
#define SRC_HEIGHT2 BlockIOTag(0x6bu)
#define SRC_HEIGHT2_WIDTH2 BlockIOTag(0x6cu)
#define SRC_CNTL BlockIOTag(0x6du)
-#define SRC_PATT_EN 0x00000001ul
-#define SRC_PATT_ROT_EN 0x00000002ul
-#define SRC_LINEAR_EN 0x00000004ul
-#define SRC_BYTE_ALIGN 0x00000008ul
-#define SRC_LINE_X_DIR 0x00000010ul
-#define SRC_8X8X8_BRUSH 0x00000020ul /* VTB/GTB */
-#define FAST_FILL_EN 0x00000040ul /* VTB/GTB */
-#define SRC_TRACK_DST 0x00000080ul /* VTB/GTB */
-#define BUS_MASTER_EN 0x00000100ul /* VTB/GTB */
-#define BUS_MASTER_SYNC 0x00000200ul /* VTB/GTB */
-#define BUS_MASTER_OP 0x00000c00ul /* VTB/GTB */
-#define SRC_8X8X8_BRUSH_LOADED 0x00001000ul /* VTB/GTB */
-#define COLOR_REG_WRITE_EN 0x00002000ul /* VTB/GTB */
-#define BLOCK_WRITE_EN 0x00004000ul /* VTB/GTB */
+# define SRC_PATT_EN 0x00000001ul
+# define SRC_PATT_ROT_EN 0x00000002ul
+# define SRC_LINEAR_EN 0x00000004ul
+# define SRC_BYTE_ALIGN 0x00000008ul
+# define SRC_LINE_X_DIR 0x00000010ul
+# define SRC_8X8X8_BRUSH 0x00000020ul /* VTB/GTB */
+# define FAST_FILL_EN 0x00000040ul /* VTB/GTB */
+# define SRC_TRACK_DST 0x00000080ul /* VTB/GTB */
+# define BUS_MASTER_EN 0x00000100ul /* VTB/GTB */
+# define BUS_MASTER_SYNC 0x00000200ul /* VTB/GTB */
+# define BUS_MASTER_OP 0x00000c00ul /* VTB/GTB */
+# define BM_OP_FRAME_TO_SYSTEM (0 << 10)
+# define BM_OP_SYSTEM_TO_FRAME (1 << 10)
+# define BM_OP_REG_TO_SYSTEM (2 << 10)
+# define BM_OP_SYSTEM_TO_REG (3 << 10)
+# define SRC_8X8X8_BRUSH_LOADED 0x00001000ul /* VTB/GTB */
+# define COLOR_REG_WRITE_EN 0x00002000ul /* VTB/GTB */
+# define BLOCK_WRITE_EN 0x00004000ul /* VTB/GTB */
/* ? 0xffff8000ul */
/* ? BlockIOTag(0x6eu) */
/* ? BlockIOTag(0x6fu) */
@@ -1348,6 +1353,11 @@
#define BM_ADDR BlockIOTag(0x92u) /* VTB/GTB */
#define BM_DATA BlockIOTag(0x92u) /* VTB/GTB */
#define BM_GUI_TABLE_CMD BlockIOTag(0x93u) /* GTPro */
+# define CIRCULAR_BUF_SIZE_16KB (0 << 0)
+# define CIRCULAR_BUF_SIZE_32KB (1 << 0)
+# define CIRCULAR_BUF_SIZE_64KB (2 << 0)
+# define CIRCULAR_BUF_SIZE_128KB (3 << 0)
+# define LAST_DESCRIPTOR (1 << 31)
/* ? BlockIOTag(0x94u) */
/* ? BlockIOTag(0x95u) */
/* ? BlockIOTag(0x96u) */
@@ -1409,21 +1419,57 @@
#define DP_C14_RGB_HIGH_NIBBLE 0x08000000ul /* GTB */
#define DP_SCALE_PIX_WIDTH 0xf0000000ul /* GTB */
#define DP_MIX BlockIOTag(0xb5u)
-#define DP_BKGD_MIX 0x0000001ful
-/* ? 0x0000ffe0ul */
-#define DP_FRGD_MIX 0x001f0000ul
-/* ? 0xffe00000ul */
+# define BKGD_MIX_NOT_D (0 << 0)
+# define BKGD_MIX_ZERO (1 << 0)
+# define BKGD_MIX_ONE (2 << 0)
+# define BKGD_MIX_D (3 << 0)
+# define BKGD_MIX_NOT_S (4 << 0)
+# define BKGD_MIX_D_XOR_S (5 << 0)
+# define BKGD_MIX_NOT_D_XOR_S (6 << 0)
+# define BKGD_MIX_S (7 << 0)
+# define BKGD_MIX_NOT_D_OR_NOT_S (8 << 0)
+# define BKGD_MIX_D_OR_NOT_S (9 << 0)
+# define BKGD_MIX_NOT_D_OR_S (10 << 0)
+# define BKGD_MIX_D_OR_S (11 << 0)
+# define BKGD_MIX_D_AND_S (12 << 0)
+# define BKGD_MIX_NOT_D_AND_S (13 << 0)
+# define BKGD_MIX_D_AND_NOT_S (14 << 0)
+# define BKGD_MIX_NOT_D_AND_NOT_S (15 << 0)
+# define BKGD_MIX_D_PLUS_S_DIV2 (23 << 0)
+# define FRGD_MIX_NOT_D (0 << 16)
+# define FRGD_MIX_ZERO (1 << 16)
+# define FRGD_MIX_ONE (2 << 16)
+# define FRGD_MIX_D (3 << 16)
+# define FRGD_MIX_NOT_S (4 << 16)
+# define FRGD_MIX_D_XOR_S (5 << 16)
+# define FRGD_MIX_NOT_D_XOR_S (6 << 16)
+# define FRGD_MIX_S (7 << 16)
+# define FRGD_MIX_NOT_D_OR_NOT_S (8 << 16)
+# define FRGD_MIX_D_OR_NOT_S (9 << 16)
+# define FRGD_MIX_NOT_D_OR_S (10 << 16)
+# define FRGD_MIX_D_OR_S (11 << 16)
+# define FRGD_MIX_D_AND_S (12 << 16)
+# define FRGD_MIX_NOT_D_AND_S (13 << 16)
+# define FRGD_MIX_D_AND_NOT_S (14 << 16)
+# define FRGD_MIX_NOT_D_AND_NOT_S (15 << 16)
+# define FRGD_MIX_D_PLUS_S_DIV2 (23 << 16)
#define DP_SRC BlockIOTag(0xb6u)
-#define DP_BKGD_SRC 0x00000007ul
-/* ? 0x000000feul */
-#define DP_FRGD_SRC 0x00000700ul
-/* ? 0x0000fe00ul */
-#define DP_MONO_SRC 0x00030000ul
-#define DP_MONO_SRC_ALLONES 0x00000000ul
-#define DP_MONO_SRC_PATTERN 0x00010000ul
-#define DP_MONO_SRC_HOST 0x00020000ul
-#define DP_MONO_SRC_BLIT 0x00030000ul
-/* ? 0xfffc0000ul */
+# define BKGD_SRC_BKGD_CLR (0 << 0)
+# define BKGD_SRC_FRGD_CLR (1 << 0)
+# define BKGD_SRC_HOST (2 << 0)
+# define BKGD_SRC_BLIT (3 << 0)
+# define BKGD_SRC_PATTERN (4 << 0)
+# define BKGD_SRC_3D (5 << 0)
+# define FRGD_SRC_BKGD_CLR (0 << 8)
+# define FRGD_SRC_FRGD_CLR (1 << 8)
+# define FRGD_SRC_HOST (2 << 8)
+# define FRGD_SRC_BLIT (3 << 8)
+# define FRGD_SRC_PATTERN (4 << 8)
+# define FRGD_SRC_3D (5 << 8)
+# define MONO_SRC_ONE (0 << 16)
+# define MONO_SRC_PATTERN (1 << 16)
+# define MONO_SRC_HOST (2 << 16)
+# define MONO_SRC_BLIT (3 << 16)
#define DP_FRGD_CLR_MIX BlockIOTag(0xb7u) /* VTB/GTB */
#define DP_FRGD_BKGD_CLR BlockIOTag(0xb8u) /* VTB/GTB */
/* ? BlockIOTag(0xb9u) */
@@ -1677,12 +1723,16 @@
#define GUI_CMDFIFO_DEBUG BlockIOTag(0x15cu) /* GT2c/VT4 */
#define GUI_CMDFIFO_DATA BlockIOTag(0x15du) /* GT2c/VT4 */
#define GUI_CNTL BlockIOTag(0x15eu) /* GT2c/VT4 */
-#define CMDFIFO_SIZE_MODE 0x00000003ul
+# define CMDFIFO_SIZE_MASK 0x00000003ul
+# define CMDFIFO_SIZE_192 0x00000000ul
+# define CMDFIFO_SIZE_128 0x00000001ul
+# define CMDFIFO_SIZE_64 0x00000002ul
/* ? 0x0000fffcul */
-#define IDCT_PRSR_MODE 0x00010000ul /* XL/XC */
-#define IDCT_BLOCK_GUI_INITIATOR 0x00020000ul /* XL/XC */
+# define IDCT_PRSR_MODE 0x00010000ul /* XL/XC */
+# define IDCT_BLOCK_GUI_INITIATOR 0x00020000ul /* XL/XC */
/* ? 0xfffc0000ul */
/* ? BlockIOTag(0x15fu) */
+/* BUS MASTERING */
#define BM_FRAME_BUF_OFFSET BlockIOTag(0x160u) /* VTB/GTB */
#define BM_SYSTEM_MEM_ADDR BlockIOTag(0x161u) /* VTB/GTB */
#define BM_COMMAND BlockIOTag(0x162u) /* VTB/GTB */
@@ -1699,6 +1749,14 @@
/* ? BlockIOTag(0x16du) */
#define BM_GUI_TABLE BlockIOTag(0x16eu) /* VTB/GTB */
#define BM_SYSTEM_TABLE BlockIOTag(0x16fu) /* VTB/GTB */
+# define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff
+# define DMA_GUI_COMMAND__HOLD_VIDEO_OFFSET 0x40000000
+# define DMA_GUI_COMMAND__EOL 0x80000000
+# define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0
+# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1
+# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF0_READY 0x2
+# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF1_READY 0x3
+# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_SNAPSHOT_READY 0x4
/* ? BlockIOTag(0x170u) */
/* ? BlockIOTag(0x171u) */
/* ? BlockIOTag(0x172u) */
Index: mach64_vid.c
===================================================================
RCS file: /cvsroot/mplayer/main/vidix/drivers/mach64_vid.c,v
retrieving revision 1.26
retrieving revision 1.27
diff -u -r1.26 -r1.27
--- mach64_vid.c 23 Apr 2002 01:31:01 -0000 1.26
+++ mach64_vid.c 31 May 2002 23:17:43 -0000 1.27
@@ -440,7 +440,6 @@
}
}
-
int vixInit(void)
{
int err;
@@ -867,19 +866,32 @@
int vixConfigPlayback(vidix_playback_t *info)
{
+ unsigned rgb_size,nfr;
if(!is_supported_fourcc(info->fourcc)) return ENOSYS;
+ if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES;
mach64_compute_framesize(info);
-
- if(info->num_frames>4) info->num_frames=4;
- for(;info->num_frames>0; info->num_frames--)
+ rgb_size = mach64_get_xres()*mach64_get_yres()*((mach64_vid_get_dbpp()+7)/8);
+ nfr = info->num_frames;
+ for(;nfr>0;nfr--)
{
- mach64_overlay_offset = mach64_ram_size - info->frame_size*info->num_frames;
+ mach64_overlay_offset = mach64_ram_size - info->frame_size*nfr;
mach64_overlay_offset &= 0xffff0000;
- if(mach64_overlay_offset>0) break;
+ if(mach64_overlay_offset >= (int)rgb_size ) break;
}
- if(info->num_frames <= 0) return EINVAL;
-
+ if(nfr <= 3)
+ {
+ nfr = info->num_frames;
+ for(;nfr>0;nfr--)
+ {
+ mach64_overlay_offset = mach64_ram_size - info->frame_size*nfr;
+ mach64_overlay_offset &= 0xffff0000;
+ if(mach64_overlay_offset>=0) break;
+ }
+ }
+ if(nfr <= 0) return EINVAL;
+ info->num_frames=nfr;
+ num_mach64_buffers = info->num_frames;
info->dga_addr = (char *)mach64_mem_base + mach64_overlay_offset;
mach64_vid_init_video(info);
return 0;
@@ -887,8 +899,15 @@
int vixPlaybackOn(void)
{
+ int err;
mach64_vid_display_video();
- return 0;
+ err = INREG(SCALER_BUF_PITCH) == besr.vid_buf_pitch ? 0 : EINTR;
+ if(err)
+ {
+ printf("[mach64] *** Internal fatal error ***: Detected pitch corruption\n"
+ "[mach64] Try decrease number of buffers\n");
+ }
+ return err;
}
int vixPlaybackOff(void)
@@ -908,12 +927,12 @@
deinterlacing and TV-in
*/
if(num_mach64_buffers==1) return 0;
-
for(i=0; i<3; i++)
{
off[i] = mach64_buffer_base[frame][i];
off[i+3]= mach64_buffer_base[last_frame][i];
}
+ if(__verbose > VERBOSE_LEVEL) printf("mach64_vid: flip_page = %u\n",frame);
#if 0 // delay routine so the individual frames can be ssen better
{
Index: radeon.h
===================================================================
RCS file: /cvsroot/mplayer/main/vidix/drivers/radeon.h,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -r1.7 -r1.8
--- radeon.h 11 Mar 2002 08:48:54 -0000 1.7
+++ radeon.h 31 May 2002 23:17:43 -0000 1.8
@@ -63,6 +63,15 @@
#define CONFIG_CNTL 0x00E0
/* CONFIG_CNTL bit constants */
# define CFG_VGA_RAM_EN 0x00000100
+#ifdef RAGE128
+#define GEN_RESET_CNTL 0x00f0
+# define SOFT_RESET_GUI 0x00000001
+# define SOFT_RESET_VCLK 0x00000100
+# define SOFT_RESET_PCLK 0x00000200
+# define SOFT_RESET_ECP 0x00000400
+# define SOFT_RESET_DISPENG_XCLK 0x00000800
+# define SOFT_RESET_MEMCTLR_XCLK 0x00001000
+#endif
#define CONFIG_MEMSIZE 0x00F8
#define CONFIG_APER_0_BASE 0x0100
#define CONFIG_APER_1_BASE 0x0104
@@ -85,7 +94,7 @@
#define AMCGPIO_EN_REG 0x01a8
#define AMCGPIO_MASK 0x0194
#define AMCGPIO_Y_REG 0x01a4
-#define BM_STATUS 0x0160
+/*#define BM_STATUS 0x0160*/
#define MPP_TB_CONFIG 0x01c0 /* ? */
#define MPP_GP_CONFIG 0x01c8 /* ? */
#define VENDOR_ID 0x0F00
@@ -200,10 +209,21 @@
#define MEM_INIT_LATENCY_TIMER 0x0154
#define MEM_SDRAM_MODE_REG 0x0158
#define AGP_BASE 0x0170
+#ifdef RAGE128
+#define PCI_GART_PAGE 0x017c
+#define PC_NGUI_MODE 0x0180
+#define PC_NGUI_CTLSTAT 0x0184
+# define PC_FLUSH_GUI (3 << 0)
+# define PC_RI_GUI (1 << 2)
+# define PC_FLUSH_ALL 0x00ff
+# define PC_BUSY (1 << 31)
+#define PC_MISC_CNTL 0x0188
+#else
#define MEM_IO_CNTL_A1 0x017C
#define MEM_IO_CNTL_B0 0x0180
#define MEM_IO_CNTL_B1 0x0184
#define MC_DEBUG 0x0188
+#endif
#define MC_STATUS 0x0150
#define MEM_IO_OE_CNTL 0x018C
#define MC_FB_LOCATION 0x0148
@@ -554,7 +574,9 @@
# define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */
# define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */
# define SCALER_DIS_LIMIT 0x08000000L
+#ifdef RAGE128
# define SCALER_PRG_LOAD_START 0x10000000L
+#endif
# define SCALER_INT_EMU 0x20000000L
# define SCALER_ENABLE 0x40000000L
# define SCALER_SOFT_RESET 0x80000000L
@@ -686,6 +708,18 @@
#define OV0_GRAPHICS_KEY_CLR 0x04EC
#define OV0_GRAPHICS_KEY_MSK 0x04F0
#define OV0_KEY_CNTL 0x04F4
+#ifdef RAGE128
+# define VIDEO_KEY_FN_MASK 0x00000007L
+# define VIDEO_KEY_FN_FALSE 0x00000000L
+# define VIDEO_KEY_FN_TRUE 0x00000001L
+# define VIDEO_KEY_FN_EQ 0x00000004L
+# define VIDEO_KEY_FN_NE 0x00000005L
+# define GRAPHIC_KEY_FN_MASK 0x00000070L
+# define GRAPHIC_KEY_FN_FALSE 0x00000000L
+# define GRAPHIC_KEY_FN_TRUE 0x00000010L
+# define GRAPHIC_KEY_FN_EQ 0x00000040L
+# define GRAPHIC_KEY_FN_NE 0x00000050L
+#else
# define VIDEO_KEY_FN_MASK 0x00000003L
# define VIDEO_KEY_FN_FALSE 0x00000000L
# define VIDEO_KEY_FN_TRUE 0x00000001L
@@ -696,6 +730,7 @@
# define GRAPHIC_KEY_FN_TRUE 0x00000010L
# define GRAPHIC_KEY_FN_EQ 0x00000020L
# define GRAPHIC_KEY_FN_NE 0x00000030L
+#endif
# define CMP_MIX_MASK 0x00000100L
# define CMP_MIX_OR 0x00000000L
# define CMP_MIX_AND 0x00000100L
@@ -783,6 +818,9 @@
#define SCRATCH_UMSK 0x0770
#define SCRATCH_ADDR 0x0774
#define DMA_GUI_TABLE_ADDR 0x0780
+# define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff
+# define DMA_GUI_COMMAND__INTDIS 0x40000000
+# define DMA_GUI_COMMAND__EOL 0x80000000
#define DMA_GUI_SRC_ADDR 0x0784
#define DMA_GUI_DST_ADDR 0x0788
#define DMA_GUI_COMMAND 0x078C
@@ -990,6 +1028,11 @@
#define DST_Y_X 0x1438
#define DST_WIDTH_HEIGHT 0x1598
#define DST_HEIGHT_WIDTH 0x143c
+#ifdef RAGE128
+#define GUI_STAT 0x1740
+# define GUI_FIFOCNT_MASK 0x0fff
+# define GUI_ACTIVE (1 << 31)
+#endif
#define SRC_CLUT_ADDRESS 0x1780
#define SRC_CLUT_DATA 0x1784
#define SRC_CLUT_DATA_RD 0x1788
@@ -1195,13 +1238,29 @@
#define PPLL_DIV_2 0x0006
#define PPLL_DIV_3 0x0007
#define VCLK_ECP_CNTL 0x0008
+# define VCLK_SRC_SEL_MASK 0x03
+# define VCLK_SRC_SEL_CPUCLK 0x00
+# define VCLK_SRC_SEL_PSCANCLK 0x01
+# define VCLK_SRC_SEL_BYTECLK 0x02
+# define VCLK_SRC_SEL_PPLLCLK 0x03
#define HTOTAL_CNTL 0x0009
#define HTOTAL2_CNTL 0x002e /* PLL */
#define M_SPLL_REF_FB_DIV 0x000a
#define AGP_PLL_CNTL 0x000b
#define SPLL_CNTL 0x000c
#define SCLK_CNTL 0x000d
+# define DYN_STOP_LAT_MASK 0x00007ff8
+# define CP_MAX_DYN_STOP_LAT 0x0008
+# define SCLK_FORCEON_MASK 0xffff8000
+#define SCLK_MORE_CNTL 0x0035 /* PLL */
+# define SCLK_MORE_FORCEON 0x0700
#define MPLL_CNTL 0x000e
+#ifdef RAGE128
+#define MCLK_CNTL 0x000f /* PLL */
+# define FORCE_GCP (1 << 16)
+# define FORCE_PIPE3D_CP (1 << 17)
+# define FORCE_RCP (1 << 18)
+#else
#define MCLK_CNTL 0x0012
/* MCLK_CNTL bit constants */
# define FORCEON_MCLKA (1 << 16)
@@ -1210,6 +1269,7 @@
# define FORCEON_YCLKB (1 << 19)
# define FORCEON_MC (1 << 20)
# define FORCEON_AIC (1 << 21)
+#endif
#define PLL_TEST_CNTL 0x0013
#define P2PLL_CNTL 0x002a /* P2PLL */
# define P2PLL_RESET (1 << 0)
@@ -1224,6 +1284,12 @@
# define P2PLL_REF_DIV_MASK 0x03ff
# define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */
# define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */
+#define PIXCLKS_CNTL 0x002d
+# define PIX2CLK_SRC_SEL_MASK 0x03
+# define PIX2CLK_SRC_SEL_CPUCLK 0x00
+# define PIX2CLK_SRC_SEL_PSCANCLK 0x01
+# define PIX2CLK_SRC_SEL_BYTECLK 0x02
+# define PIX2CLK_SRC_SEL_P2PLLCLK 0x03
/* masks */
@@ -1236,15 +1302,43 @@
#define PPLL_FB3_DIV_MASK 0x000007ff
#define PPLL_POST3_DIV_MASK 0x00070000
-#define GUI_ACTIVE 0x80000000
+/* BUS MASTERING */
+#define BM_FRAME_BUF_OFFSET 0xA00
+#define BM_SYSTEM_MEM_ADDR 0xA04
+#define BM_COMMAND 0xA08
+# define BM_INTERRUPT_DIS 0x08000000
+# define BM_TRANSFER_DEST_REG 0x10000000
+# define BM_FORCE_TO_PCI 0x20000000
+# define BM_FRAME_OFFSET_HOLD 0x40000000
+# define BM_END_OF_LIST 0x80000000
+#define BM_STATUS 0xA0c
+#define BM_QUEUE_STATUS 0xA10
+#define BM_QUEUE_FREE_STATUS 0xA14
+#define BM_CHUNK_0_VAL 0xA18
+# define BM_PTR_FORCE_TO_PCI 0x00200000
+# define BM_PM4_RD_FORCE_TO_PCI 0x00400000
+# define BM_GLOBAL_FORCE_TO_PCI 0x00800000
+# define BM_VIP3_NOCHUNK 0x10000000
+# define BM_VIP2_NOCHUNK 0x20000000
+# define BM_VIP1_NOCHUNK 0x40000000
+# define BM_VIP0_NOCHUNK 0x80000000
+#define BM_CHUNK_1_VAL 0xA1C
+#define BM_VIP0_BUF 0xA20
+# define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0
+# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1
+#define BM_VIP0_ACTIVE 0xA24
+#define BM_VIP1_BUF 0xA30
+#define BM_VIP1_ACTIVE 0xA34
+#define BM_VIP2_BUF 0xA40
+#define BM_VIP2_ACTIVE 0xA44
+#define BM_VIP3_BUF 0xA50
+#define BM_VIP3_ACTIVE 0xA54
+#define BM_VIDCAP_BUF0 0xA60
+#define BM_VIDCAP_BUF1 0xA64
+#define BM_VIDCAP_BUF2 0xA68
+#define BM_VIDCAP_ACTIVE 0xA6c
+#define BM_GUI 0xA80
-/* GEN_RESET_CNTL bit constants */
-#define SOFT_RESET_GUI 0x00000001
-#define SOFT_RESET_VCLK 0x00000100
-#define SOFT_RESET_PCLK 0x00000200
-#define SOFT_RESET_ECP 0x00000400
-#define SOFT_RESET_DISPENG_XCLK 0x00000800
-
/* RAGE THEATER REGISTERS */
#define DMA_VIPH0_COMMAND 0x0A00
Index: radeon_vid.c
===================================================================
RCS file: /cvsroot/mplayer/main/vidix/drivers/radeon_vid.c,v
retrieving revision 1.46
retrieving revision 1.47
diff -u -r1.46 -r1.47
--- radeon_vid.c 17 Mar 2002 16:08:39 -0000 1.46
+++ radeon_vid.c 31 May 2002 23:17:43 -0000 1.47
@@ -280,6 +280,49 @@
}
}
+#ifdef RAGE128
+static void _radeon_engine_idle(void);
+static void _radeon_fifo_wait(unsigned);
+#define radeon_engine_idle() _radeon_engine_idle()
+#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries)
+/* Flush all dirty data in the Pixel Cache to memory. */
+static __inline__ void radeon_engine_flush ( void )
+{
+ unsigned i;
+
+ OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL);
+ for (i = 0; i < 2000000; i++) {
+ if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break;
+ }
+}
+
+/* Reset graphics card to known state. */
+static void radeon_engine_reset( void )
+{
+ uint32_t clock_cntl_index;
+ uint32_t mclk_cntl;
+ uint32_t gen_reset_cntl;
+
+ radeon_engine_flush();
+
+ clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
+ mclk_cntl = INPLL(MCLK_CNTL);
+
+ OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP);
+
+ gen_reset_cntl = INREG(GEN_RESET_CNTL);
+
+ OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
+ INREG(GEN_RESET_CNTL);
+ OUTREG(GEN_RESET_CNTL,
+ gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI));
+ INREG(GEN_RESET_CNTL);
+
+ OUTPLL(MCLK_CNTL, mclk_cntl);
+ OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
+ OUTREG(GEN_RESET_CNTL, gen_reset_cntl);
+}
+#else
static __inline__ void radeon_engine_flush ( void )
{
@@ -345,9 +388,10 @@
return;
}
-
+#endif
static void radeon_engine_restore( void )
{
+#ifndef RAGE128
int pitch64;
uint32_t xres,yres,bpp;
radeon_fifo_wait(1);
@@ -389,16 +433,17 @@
OUTREG(DP_WRITE_MASK, 0xffffffff);
radeon_engine_idle();
+#endif
}
-
+#ifdef RAGE128
static void _radeon_fifo_wait (unsigned entries)
{
- int i;
+ unsigned i;
for(;;)
{
for (i=0; i<2000000; i++)
- if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries)
+ if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries)
return;
radeon_engine_reset();
radeon_engine_restore();
@@ -407,14 +452,14 @@
static void _radeon_engine_idle ( void )
{
- int i;
+ unsigned i;
/* ensure FIFO is empty before waiting for idle */
radeon_fifo_wait (64);
for(;;)
{
for (i=0; i<2000000; i++) {
- if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
+ if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) {
radeon_engine_flush ();
return;
}
@@ -423,8 +468,39 @@
radeon_engine_restore();
}
}
+#else
+static void _radeon_fifo_wait (unsigned entries)
+{
+ unsigned i;
+ for(;;)
+ {
+ for (i=0; i<2000000; i++)
+ if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries)
+ return;
+ radeon_engine_reset();
+ radeon_engine_restore();
+ }
+}
+static void _radeon_engine_idle ( void )
+{
+ int i;
+ /* ensure FIFO is empty before waiting for idle */
+ radeon_fifo_wait (64);
+ for(;;)
+ {
+ for (i=0; i<2000000; i++) {
+ if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) {
+ radeon_engine_flush ();
+ return;
+ }
+ }
+ radeon_engine_reset();
+ radeon_engine_restore();
+ }
+}
+#endif
#ifndef RAGE128
/* Reference color space transform data */
@@ -1064,6 +1140,10 @@
if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy;
else pitch = 32;
break;
+ case IMGFMT_YVU9:
+ if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy;
+ else pitch = 64;
+ break;
default:
if(spy >= 16) pitch = spy;
else pitch = 16;
@@ -1099,6 +1179,7 @@
mpitch = best_pitch-1;
switch(config->fourcc)
{
+ case IMGFMT_YVU9:
/* 4:2:0 */
case IMGFMT_IYUV:
case IMGFMT_YV12:
@@ -1125,11 +1206,10 @@
dest_w = config->dest.w;
dest_h = config->dest.h;
if(radeon_is_dbl_scan()) dest_h *= 2;
- else
- if(radeon_is_interlace()) dest_h /= 2;
besr.dest_bpp = radeon_vid_get_dbpp();
besr.fourcc = config->fourcc;
besr.v_inc = (src_h << 20) / dest_h;
+ if(radeon_is_interlace()) besr.v_inc *= 2;
h_inc = (src_w << 12) / dest_w;
step_by = 1;
while(h_inc >= (2 << 12)) {
@@ -1236,46 +1316,50 @@
case IMGFMT_YV12:
case IMGFMT_IYUV:
awidth = (info->src.w + (pitch-1)) & ~(pitch-1);
- info->frame_size = (awidth*(info->src.h+info->src.h/2)+dbpp-1)/dbpp;
+ info->frame_size = awidth*(info->src.h+info->src.h/2);
break;
case IMGFMT_RGB32:
case IMGFMT_BGR32:
awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1);
- info->frame_size = ((awidth*info->src.h)+dbpp-1)/dbpp;
+ info->frame_size = awidth*info->src.h;
break;
/* YUY2 YVYU, RGB15, RGB16 */
default:
awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1);
- info->frame_size = ((awidth*info->src.h)+dbpp-1)/dbpp;
+ info->frame_size = awidth*info->src.h;
break;
}
- info->frame_size *= dbpp;
}
int vixConfigPlayback(vidix_playback_t *info)
{
- unsigned rgb_size;
+ unsigned rgb_size,nfr;
if(!is_supported_fourcc(info->fourcc)) return ENOSYS;
- if(info->num_frames>=VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES-1;
+ if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES;
if(info->num_frames==1) besr.double_buff=0;
else besr.double_buff=1;
radeon_compute_framesize(info);
- rgb_size = radeon_get_xres()*radeon_get_yres()*radeon_vid_get_dbpp();
- for(;info->num_frames>0; info->num_frames--)
+ rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8);
+ nfr = info->num_frames;
+ for(;nfr>0; nfr--)
{
- radeon_overlay_off = radeon_ram_size - info->frame_size*info->num_frames;
+ radeon_overlay_off = radeon_ram_size - info->frame_size*nfr;
radeon_overlay_off &= 0xffff0000;
if(radeon_overlay_off >= (int)rgb_size ) break;
}
- if(info->num_frames <= 3)
- for(;info->num_frames>0; info->num_frames--)
+ if(nfr <= 3)
+ {
+ nfr = info->num_frames;
+ for(;nfr>0; nfr--)
{
- radeon_overlay_off = radeon_ram_size - info->frame_size*info->num_frames;
+ radeon_overlay_off = radeon_ram_size - info->frame_size*nfr;
radeon_overlay_off &= 0xffff0000;
if(radeon_overlay_off > 0) break;
}
- if(info->num_frames <= 0) return EINVAL;
+ }
+ if(nfr <= 0) return EINVAL;
+ info->num_frames = nfr;
besr.vid_nbufs = info->num_frames;
info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off;
radeon_vid_init_video(info);
@@ -1453,9 +1537,10 @@
{
if(radeon_grkey.ckey.op == CKEY_TRUE)
{
+ int dbpp=radeon_vid_get_dbpp();
besr.ckey_on=1;
- switch(radeon_vid_get_dbpp())
+ switch(dbpp)
{
case 15:
besr.graphics_key_clr=
@@ -1486,8 +1571,13 @@
besr.graphics_key_msk=0;
besr.graphics_key_clr=0;
}
- besr.graphics_key_msk = besr.graphics_key_clr;
+#ifdef RAGE128
+ besr.graphics_key_msk=(1<<dbpp)-1;
+ besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND;
+#else
+ besr.graphics_key_msk=besr.graphics_key_clr;
besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND;
+#endif
}
else
{
