[Mplayer-users] [mplayer-20010411 PATCH] Fix MMX2 support

Nick Kurshev nickols_k at mail.ru
Fri Apr 13 14:09:13 CEST 2001


>> I'm sorry! In previous patch I sent you version that is workable only on K7 cpu.
>> (instruction PREFETCH exists only on K6-2, K7 cpus. Full analog of it is
>> that exists on both K7 and P3 processors).
>I don't really understand...
>I've tried the PREFETCH version on celeron-2 and it worked!
>What's the difference between PREFETCH and PREFETCHNTA ?
>(in viewpoint of both speed and supported CPUs)

It's news for me. I refer to:
"IA-32 Intel Architecture Software Developer s Manual Volume 2 :
 Instruction Set Reference" Order Number 245471 (It's P4 manual)
This manual documents only PREFETCHx instructions with opcodes 0F 18 /x: 
PREFETCHTO - prefetch data into all cache levels.
PREFETCHT1 - prefetch data in all cache levels except 0th cache level
PREFETCHT2 - prefetch data in all cache levels, except 0th and 1st cache levels.
PREFETCHNTA - prefetch data into non-temporal cache structure. (This hint can be
used to minimize pollution of caches.)

"AMD Extensions to the 3DNow! and MMX Instruction Sets Manual"
Publication # 22466 Rev: B documents these instructions as supported by K7 cpus.

But theirs early manual: "3DNow! Technology Manual" 21928E/0 November 1998 (for K6-2)
documents only PREFETCH / PREFETCHW as 3dnow instructions with opcodes 0F 0D /x:
PREFETCH - Prefetch processor cache line into L1 data cache (Dcache)
PREFETCHW - loads the prefetched line and sets the cache line MESI
state to modified (in anticipation of subsequent data writes to the line), unlike the
PREFETCH instruction, which typically sets the state to exclusive.

I have installed binutils-2.10 and it perform 3dnow opcodes for prefetch instruction
But may be P3 (and Celeron-2) undocumentedly support 3dnow opcodes ;)

>AFAIK the mmx2 is called xmm in /proc/cpuinfo. AT least for cel2/p3 + kernel
>2.4.3. Older kernels called it kni or sse.
>Where is it called 'mmxext'?

Yes, I was wrong. It's only present on AMD processors.
In "AMD Processor Recognition Application Note" it's documented as:
AMD MMX  Instruction Extensions (bit #22 in EAX after execution CPUID with EAX=0x80000001)
and it's differ from "AMD 3DNow!  Instruction Extensions" (bit 30), "3DNow! Instructions" (bit 31)
and "MMX Instructions" (bit 23). Therefore Linux-kernel describes it as MMXEXT.
Indeed Intel P3 introduced two technology: SSE and MMX2 same as P4 introduced SSE2.
But Intel don't prefed to differ their and called their as SSE extensions. But indeed MMX2 it's extended
instruction set for old 64-bit MMX registers and it also is supported by AMD K7 cpus opposite to SSE.
It my /proc/cpuinfo:

processor	: 0
vendor_id	: AuthenticAMD
cpu family	: 6
model		: 3
model name	: AMD Duron(tm) Processor
stepping	: 1
cpu MHz	: 759.425
cache size	: 64 KB
fdiv_bug	: no
hlt_bug		: no
f00f_bug	: no
coma_bug	: no
fpu		: yes
fpu_exception	: yes
cpuid level	: 1
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 sep mtrr pge mca cmov pat pse36 mmx fxsr syscall mmxext 3dnowext 3dnow
bogomips	: 1513.88

>Thank you for patches. Do you have account at SF? (Then I can add CVS write
>access, simpler way to apply changes)
Undoubtedly, but I have no other ideas at the moment and anyway I reckon that every patch 
should be applied by author or by advance developers which are in the project a long time
and are known with all fine points of the project. But if new ideas will cross my mind I'll send
you their. 

Best regards! Nick

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