Index: TOOLS/cpuinfo.c
===================================================================
--- TOOLS/cpuinfo.c	£¨ÐÞ¶©°æ 19905£©
+++ TOOLS/cpuinfo.c	£¨¹¤×÷¿½±´£©
@@ -150,82 +150,78 @@
   if (max_cpuid >= 1) {
     static struct {
       int bit;
-      char *desc;;
-      char *description;
+      char *desc;
     } cap[] = {
-      { 0,  "fpu",   "Floating-point unit on-chip" },
-      { 1,  "vme",   "Virtual Mode Enhancements" },
-      { 2,  "de",    "Debugging Extension" },
-      { 3,  "pse",   "Page Size Extension" },
-      { 4,  "tsc",   "Time Stamp Counter" },
-      { 5,  "msr",   "Pentium Processor MSR" },
-      { 6,  "pae",   "Physical Address Extension" },
-      { 7,  "mce",   "Machine Check Exception" },
-      { 8,  "cx8",   "CMPXCHG8B Instruction Supported" },
-      { 9,  "apic",  "On-chip APIC Hardware Enabled" },
-      { 11, "sep",   "SYSENTER and SYSEXIT" },
-      { 12, "mtrr",  "Memory Type Range Registers" },
-      { 13, "pge",   "PTE Global Bit" },
-      { 14, "mca",   "Machine Check Architecture" },
-      { 15, "cmov",  "Conditional Move/Compare Instruction" },
-      { 16, "pat",   "Page Attribute Table" },
-      { 17, "pse36", "Page Size Extension 36-bit" },
-      { 18, "pn",    "Processor Serial Number" },
-      { 19, "cflsh", "CFLUSH instruction" },
-      { 21, "dts",   "Debug Store" },
-      { 22, "acpi",  "Thermal Monitor and Clock Ctrl" },
-      { 23, "mmx",   "MMX Technology" },
-      { 24, "fxsr",  "FXSAVE/FXRSTOR" },
-      { 25, "sse",   "SSE Extensions" },
-      { 26, "sse2",  "SSE2 Extensions" },
-      { 27, "ss",    "Self Snoop" },
-      { 28, "ht",    "Multi-threading" },
-      { 29, "tm",    "Therm. Monitor" },
-      { 30, "ia64",  "IA-64 Processor" },
-      { 31, "pbe",   "Pend. Brk. EN." },
+      { 0,  "fpu" }, /* "Floating-point unit on-chip" */
+      { 1,  "vme" }, /* "Virtual Mode Enhancements" */
+      { 2,  "de" }, /* "Debugging Extension" */
+      { 3,  "pse" }, /* "Page Size Extension" */
+      { 4,  "tsc" }, /* "Time Stamp Counter" */
+      { 5,  "msr" }, /* "Pentium Processor MSR" */
+      { 6,  "pae" }, /* "Physical Address Extension" */
+      { 7,  "mce" }, /* "Machine Check Exception" */
+      { 8,  "cx8" }, /* "CMPXCHG8B Instruction Supported" */
+      { 9,  "apic" }, /* "On-chip APIC Hardware Enabled" */
+      { 11, "sep" }, /* "SYSENTER and SYSEXIT" */
+      { 12, "mtrr" }, /* "Memory Type Range Registers" */
+      { 13, "pge" }, /* "PTE Global Bit" */
+      { 14, "mca" }, /* "Machine Check Architecture" */
+      { 15, "cmov" }, /* "Conditional Move/Compare Instruction" */
+      { 16, "pat" }, /* "Page Attribute Table" */
+      { 17, "pse36" }, /* "Page Size Extension 36-bit" */
+      { 18, "pn" }, /* "Processor Serial Number" */
+      { 19, "cflsh" }, /* "CFLUSH instruction" */
+      { 21, "dts" }, /* "Debug Store" */
+      { 22, "acpi" }, /* "Thermal Monitor and Clock Ctrl" */
+      { 23, "mmx" }, /* "MMX Technology" */
+      { 24, "fxsr" }, /* "FXSAVE/FXRSTOR" */
+      { 25, "sse" }, /* "SSE Extensions" */
+      { 26, "sse2" }, /* "SSE2 Extensions" */
+      { 27, "ss" }, /* "Self Snoop" */
+      { 28, "ht" }, /* "Multi-threading" */
+      { 29, "tm" }, /* "Therm. Monitor" */
+      { 30, "ia64" }, /* "IA-64 Processor" */
+      { 31, "pbe" }, /* "Pend. Brk. EN." */
       { -1 }
     };
     static struct {
       int bit;
       char *desc;
-      char *description;
     } cap2[] = {
-      { 0, "pni", "SSE3 Extensions" },
-      { 3, "monitor", "MONITOR/MWAIT" },
-      { 4, "ds_cpl", "CPL Qualified Debug Store" },
-      { 5, "vmx", "Virtual Machine Extensions" },
-      { 7, "est", "Enhanced Intel SpeedStep Technology" },
-      { 8, "tm2", "Thermal Monitor 2" },
-      { 10, "cid", "L1 Context ID" },
-      { 13, "cx16", "CMPXCHG16B Available" },
-      { 14, "xtpr", "xTPR Disable" }, 
+      { 0, "pni" }, /* "SSE3 Extensions" */
+      { 3, "monitor" }, /* "MONITOR/MWAIT" */
+      { 4, "ds_cpl" }, /* "CPL Qualified Debug Store" */
+      { 5, "vmx" }, /* "Virtual Machine Extensions" */
+      { 7, "est" }, /* "Enhanced Intel SpeedStep Technology" */
+      { 8, "tm2" }, /* "Thermal Monitor 2" */
+      { 10, "cid" }, /* "L1 Context ID" */
+      { 13, "cx16" }, /* "CMPXCHG16B Available" */
+      { 14, "xtpr" }, /* "xTPR Disable" */ 
       { -1 }
     };
     static struct {
       int bit;
-      char *desc;;
-      char *description;
+      char *desc;
     } cap_amd[] = {
-      { 11, "syscall", "SYSCALL and SYSRET" },
-      { 19, "mp", "MP Capable" },
-      { 20, "nx", "No-Execute Page Protection" },
-      { 22, "mmxext","MMX Technology (AMD Extensions)" },
-      { 25, "fxsr_opt", "Fast FXSAVE/FXRSTOR" },
-      { 27, "rdtscp", "RDTSCP Instruction" },
-      { 29, "lm", "Long Mode Capable" },
-      { 30, "3dnowext","3DNow! Extensions" },
-      { 31, "3dnow", "3DNow!" },
+      { 11, "syscall" }, /* "SYSCALL and SYSRET" */
+      { 19, "mp" }, /* "MP Capable" */
+      { 20, "nx" }, /* "No-Execute Page Protection" */
+      { 22, "mmxext" }, /* "MMX Technology (AMD Extensions)" */
+      { 25, "fxsr_opt" }, /* "Fast FXSAVE/FXRSTOR" */
+      { 27, "rdtscp" }, /* "RDTSCP Instruction" */
+      { 29, "lm" }, /* "Long Mode Capable" */
+      { 30, "3dnowext" }, /* "3DNow! Extensions" */
+      { 31, "3dnow" }, /* "3DNow!" */
       { -1 }
     };
     static struct {
       int bit;
       char *desc;
-      char *description;
     } cap_amd2[] = {
-      { 0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode" },
-      { 1, "cmp_legacy", "Chip Multi-Core" },
-      { 2, "svm", "Secure Virtual Machine" },
-      { 4, "cr8legacy", "CR8 Available in Legacy Mode" },
+      { 0, "lahf_lm" }, /* "LAHF/SAHF Supported in 64-bit Mode" */
+      { 1, "cmp_legacy" }, /* "Chip Multi-Core" */
+      { 2, "svm" }, /* "Secure Virtual Machine" */
+      { 4, "cr8legacy" }, /* "CR8 Available in Legacy Mode" */
       { -1 }
     };
     unsigned int family, model, stepping;