--- nvidia_vid.c.org	2005-11-09 11:10:45.000000000 -0500
+++ nvidia_vid.c	2006-02-08 00:05:06.000000000 -0500
@@ -31,7 +31,7 @@


#define MAX_FRAMES 3
-#define NV04_BES_SIZE 1024*2000*4
+#define NV04_BES_SIZE 2048*2000*4


static vidix_capability_t nvidia_cap = {
@@ -144,6 +144,7 @@
   {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30},
   {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30},
   {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30},
+  {DEVICE_NVIDIA_NV34_GEFORCE_FX3,NV_ARCH_30},
   {DEVICE_NVIDIA_NV34M_GEFORCE_FX,NV_ARCH_30},
   {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30},
   {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30},
@@ -328,7 +329,11 @@
}

static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){
-	return ((VID_RD32 (chip->PFB, 0x20C) >> 20) & 0x000000FF) * 1024 * 1024;
+	return VID_RD32 (chip->PFB, 0x20C) & 0x0FF00000;
+}
+
+static unsigned long rivatv_fbsize_nv30 (struct rivatv_chip *chip){
+	return VID_RD32 (chip->PFB, 0x20C) & 0x1FF00000;
}

//lock funcs
@@ -479,15 +484,13 @@
}

static void nv_getscreenproperties(struct rivatv_info *info){
-  uint32_t bpp=0;
+  uint32_t bpp=0,x;
   info->chip.lock(&info->chip, 0);
   /*get screen depth*/
   VID_WR08(info->chip.PCIO, 0x03D4,0x28);
   bpp = VID_RD08(info->chip.PCIO,0x03D5)&0x3;
-  if(bpp==3)bpp=4;
   if((bpp == 2) && (VID_RD32(info->chip.PVIDEO,0x600) & 0x00001000) == 
0x0)info->depth=15;
-  else info->depth = bpp*8;
-  info->bps=bpp;
+  else info->depth = 0x04 << bpp;
   /*get screen width*/
   VID_WR08(info->chip.PCIO, 0x03D4, 0x1);
   info->screen_x = (1 + VID_RD08(info->chip.PCIO, 0x3D5)) * 8;
@@ -501,6 +504,17 @@
   /* and the 10th in CRTC_OVERFLOW*/
   info->screen_y |=(VID_RD08(info->chip.PCIO,0x03D5) &0x40)<<3;
   ++info->screen_y;
+
+  /* NV_PCRTC_OFFSET */
+  VID_WR08 (info->chip.PCIO, 0x3D4, 0x13);
+  x = VID_RD08 (info->chip.PCIO, 0x3D5);
+  /* NV_PCRTC_REPAINT0_OFFSET_10_8 */
+  VID_WR08 (info->chip.PCIO, 0x3D4, 0x19);
+  x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0xE0) << 3;
+  /* NV_PCRTC_EXTRA_OFFSET_11 */
+  VID_WR08 (info->chip.PCIO, 0x3D4, 0x25);
+  x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x20) << 6; x <<= 3;
+  info->bps = x * bpp;
}


@@ -721,12 +735,17 @@
		break;
	case NV_ARCH_10:
	case NV_ARCH_20:
-	case NV_ARCH_30:
		info->chip.lock = rivatv_lock_nv04;
		info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip);
		info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000);
		info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000);
		break;
+	case NV_ARCH_30:
+		info->chip.lock = rivatv_lock_nv04;
+		info->chip.fbsize = rivatv_fbsize_nv30 (&info->chip);
+		info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000);
+		info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000);
+		break;
   }
   switch (info->chip.arch) {
	case NV_ARCH_03: