Index: swscale_template.c
===================================================================
RCS file: /cvsroot/mplayer/main/postproc/swscale_template.c,v
retrieving revision 1.114
diff -u -r1.114 swscale_template.c
--- swscale_template.c	2 Jun 2005 20:54:03 -0000	1.114
+++ swscale_template.c	26 Jun 2005 19:02:20 -0000
@@ -765,14 +765,14 @@
 		asm volatile(
 				YSCALEYUV2YV12X(0, CHR_MMX_FILTER_OFFSET)
 				:: "r" (&c->redDither),
-				"r" (uDest), "m" ((long)chrDstW)
+				 "r" (uDest), "r" ((long)chrDstW)
 				: "%"REG_a, "%"REG_d, "%"REG_S
 			);
 
 		asm volatile(
 				YSCALEYUV2YV12X(4096, CHR_MMX_FILTER_OFFSET)
 				:: "r" (&c->redDither),
-				"r" (vDest), "m" ((long)chrDstW)
+				 "r" (vDest), "r" ((long)chrDstW)
 				: "%"REG_a, "%"REG_d, "%"REG_S
 			);
 	}
@@ -780,7 +780,7 @@
 	asm volatile(
 			YSCALEYUV2YV12X(0, LUM_MMX_FILTER_OFFSET)
 			:: "r" (&c->redDither),
-			   "r" (dest), "m" ((long)dstW)
+			 "r" (dest), "r" ((long)dstW)
 			: "%"REG_a, "%"REG_d, "%"REG_S
 		);
 #else
@@ -814,14 +814,14 @@
 		asm volatile(
 				YSCALEYUV2YV121
 				:: "r" (chrSrc + chrDstW), "r" (uDest + chrDstW),
-				"g" ((long)-chrDstW)
+				"r" ((long)-chrDstW)
 				: "%"REG_a
 			);
 
 		asm volatile(
 				YSCALEYUV2YV121
 				:: "r" (chrSrc + 2048 + chrDstW), "r" (vDest + chrDstW),
-				"g" ((long)-chrDstW)
+				"r" ((long)-chrDstW)
 				: "%"REG_a
 			);
 	}
@@ -829,7 +829,7 @@
 	asm volatile(
 		YSCALEYUV2YV121
 		:: "r" (lumSrc + dstW), "r" (dest + dstW),
-		"g" ((long)-dstW)
+		"r" ((long)-dstW)
 		: "%"REG_a
 	);
 #else
@@ -1015,7 +1015,7 @@
 			" jb 1b				\n\t"
 
 
-			:: "r" (buf0), "r" (buf1), "r" (uvbuf0), "r" (uvbuf1), "r" (dest), "m" ((long)dstW),
+                        :: "r" (buf0), "r" (buf1), "r" (uvbuf0), "r" (uvbuf1), "r" (dest), "r" ((long)dstW),
 			"m" (yalpha1), "m" (uvalpha1)
 			: "%"REG_a
 			);
@@ -1064,7 +1064,7 @@
 			"cmp %5, %%"REG_a"		\n\t"
 			" jb 1b				\n\t"
 
-			:: "r" (buf0), "r" (buf1), "r" (uvbuf0), "r" (uvbuf1), "m" (dest), "m" (dstW),
+                        :: "r" (buf0), "r" (buf1), "r" (uvbuf0), "r" (uvbuf1), "m" (dest), "r" ((long)dstW),
 			"m" (yalpha1), "m" (uvalpha1)
 			: "%"REG_a, "%"REG_b
 			);
@@ -1097,7 +1097,7 @@
 			"cmp %5, %%"REG_a"		\n\t"
 			" jb 1b				\n\t"
 
-			:: "r" (buf0), "r" (buf1), "r" (uvbuf0), "r" (uvbuf1), "r" (dest), "m" (dstW),
+                        :: "r" (buf0), "r" (buf1), "r" (uvbuf0), "r" (uvbuf1), "r" (dest), "r" ((long)dstW),
 			"m" (yalpha1), "m" (uvalpha1)
 			: "%"REG_a
 			);
@@ -1130,7 +1130,7 @@
 			"cmp %5, %%"REG_a"		\n\t"
 			" jb 1b				\n\t"
 
-			:: "r" (buf0), "r" (buf1), "r" (uvbuf0), "r" (uvbuf1), "r" (dest), "m" (dstW),
+                        :: "r" (buf0), "r" (buf1), "r" (uvbuf0), "r" (uvbuf1), "r" (dest), "r" ((long)dstW),
 			"m" (yalpha1), "m" (uvalpha1)
 			: "%"REG_a
 			);
@@ -1504,7 +1504,7 @@
 		"movq %%mm0, (%2, %%"REG_a")	\n\t"
 		"add $8, %%"REG_a"		\n\t"
 		" js 1b				\n\t"
-		: : "g" ((long)-width), "r" (src+width*2), "r" (dst+width)
+		: : "r" ((long)-width), "r" (src+width*2), "r" (dst+width)
 		: "%"REG_a
 	);
 #else
@@ -1539,7 +1539,7 @@
 		"movd %%mm1, (%3, %%"REG_a")	\n\t"
 		"add $4, %%"REG_a"		\n\t"
 		" js 1b				\n\t"
-		: : "g" ((long)-width), "r" (src1+width*4), "r" (src2+width*4), "r" (dstU+width), "r" (dstV+width)
+		: : "r" ((long)-width), "r" (src1+width*4), "r" (src2+width*4), "r" (dstU+width), "r" (dstV+width)
 		: "%"REG_a
 	);
 #else
@@ -1567,7 +1567,7 @@
 		"movq %%mm0, (%2, %%"REG_a")	\n\t"
 		"add $8, %%"REG_a"		\n\t"
 		" js 1b				\n\t"
-		: : "g" ((long)-width), "r" (src+width*2), "r" (dst+width)
+		: : "r" ((long)-width), "r" (src+width*2), "r" (dst+width)
 		: "%"REG_a
 	);
 #else
@@ -1602,7 +1602,7 @@
 		"movd %%mm1, (%3, %%"REG_a")	\n\t"
 		"add $4, %%"REG_a"		\n\t"
 		" js 1b				\n\t"
-		: : "g" ((long)-width), "r" (src1+width*4), "r" (src2+width*4), "r" (dstU+width), "r" (dstV+width)
+		: : "r" ((long)-width), "r" (src1+width*4), "r" (src2+width*4), "r" (dstU+width), "r" (dstV+width)
 		: "%"REG_a
 	);
 #else
@@ -1717,7 +1717,7 @@
 		"movq %%mm0, (%1, %%"REG_a")	\n\t"
 		"add $8, %%"REG_a"		\n\t"
 		" js 1b				\n\t"
-		: : "r" (src+width*3), "r" (dst+width), "g" ((long)-width)
+		: : "r" (src+width*3), "r" (dst+width), "r" ((long)-width)
 		: "%"REG_a, "%"REG_b
 	);
 #else
@@ -1882,7 +1882,7 @@
 		"movd %%mm0, (%3, %%"REG_a")	\n\t"
 		"add $4, %%"REG_a"		\n\t"
 		" js 1b				\n\t"
-		: : "r" (src1+width*6), "r" (src2+width*6), "r" (dstU+width), "r" (dstV+width), "g" ((long)-width)
+		: : "r" (src1+width*6), "r" (src2+width*6), "r" (dstU+width), "r" (dstV+width), "r" ((long)-width)
 		: "%"REG_a, "%"REG_b
 	);
 #else
@@ -2314,8 +2314,8 @@
 	else
 	{
 #endif
-	int xInc_shr16 = xInc >> 16;
-	int xInc_mask = xInc & 0xffff;
+	long xInc_shr16 = xInc >> 16;
+	uint16_t xInc_mask = xInc & 0xffff;
 	//NO MMX just normal asm ...
 	asm volatile(
 		"xor %%"REG_a", %%"REG_a"	\n\t" // i
@@ -2353,7 +2353,7 @@
 		" jb 1b				\n\t"
 
 
-		:: "r" (src), "m" (dst), "m" (dstWidth), "m" (xInc_shr16), "m" (xInc_mask)
+		:: "r" (src), "m" (dst), "r" ((long)dstWidth), "m" (xInc_shr16), "m" (xInc_mask)
 		: "%"REG_a, "%"REG_b, "%ecx", "%"REG_D, "%esi"
 		);
 #ifdef HAVE_MMX2
@@ -2513,7 +2513,7 @@
 	{
 #endif
 	long xInc_shr16 = (long) (xInc >> 16);
-	int xInc_mask = xInc & 0xffff; 
+	uint16_t xInc_mask = xInc & 0xffff; 
 	asm volatile(
 		"xor %%"REG_a", %%"REG_a"	\n\t" // i
 		"xor %%"REG_b", %%"REG_b"		\n\t" // xx
@@ -2547,7 +2547,7 @@
 		"cmp %2, %%"REG_a"		\n\t"
 		" jb 1b				\n\t"
 
-		:: "m" (src1), "m" (dst), "m" ((long)dstWidth), "m" (xInc_shr16), "m" (xInc_mask),
+		:: "m" (src1), "m" (dst), "r" ((long)dstWidth), "m" (xInc_shr16), "m" (xInc_mask),
 		"r" (src2)
 		: "%"REG_a, "%"REG_b, "%ecx", "%"REG_D, "%esi"
 		);