--- radeon_vid.c	Thu May  2 13:30:34 2002
+++ radeon_vid_1.46_working.c	Thu May  2 13:33:17 2002
@@ -295,6 +295,13 @@
 	}
 }
 
+#ifdef RAGE128
+
+#define radeon_engine_idle()
+#define radeon_fifo_wait(entries)
+
+#else
+
 static void _radeon_engine_idle(void);
 static void _radeon_fifo_wait(unsigned);
 #define radeon_engine_idle()		_radeon_engine_idle()
@@ -423,7 +430,7 @@
 	radeon_engine_restore();
     }
 }
-
+#endif
 
 
 #ifndef RAGE128
@@ -891,7 +898,7 @@
 		    VID_DEPTH_12BPP| VID_DEPTH_15BPP|
 		    VID_DEPTH_16BPP| VID_DEPTH_24BPP|
 		    VID_DEPTH_32BPP;
-	to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
+	to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK;/* | VID_CAP_COLORKEY;*/
 	return 0;
     }
     else  to->depth = to->flags = 0;
@@ -1163,7 +1170,7 @@
 	config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off;
 	config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off;
 	config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off;
-	if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV)
+	if(/*besr.fourcc == IMGFMT_I420 ||*/ besr.fourcc == IMGFMT_IYUV)
 	{
 	  uint32_t tmp;
 	  tmp = config->offset.u;