[MPlayer-dev-eng] [PATCH] vidix nvidia_vic patch for 256M memory, bps fix etc

Pascal Yu yu_pascal at hotmail.com
Thu Feb 9 16:56:25 CET 2006


Hi,

Check my answer below.

thanks!


>From: Sascha Sommer <saschasommer at freenet.de>
>Reply-To: mplayer-dev-eng at mplayerhq.hu
>To: mplayer-dev-eng at mplayerhq.hu
>Subject: Re: [MPlayer-dev-eng] [PATCH] vidix nvidia_vic patch for 256M 
>memory,bps fix etc
>Date: Thu, 9 Feb 2006 14:11:23 +0100
>
>Hi
>
>On Wednesday 08 February 2006 06:36, Pascal Yu wrote:
> > Attached is the patch for nvidia_vid vidix driver fix for 256M VRAM. 
>256M
> > card will not show 0 MB any more.
> > Also add fix for bps, (byte per stride, not bpp byte per pixel).
> > Along with this added device ID for Geforce FX5500 in pci.db file.
> >
> > The diagonally lines issue I mentioned earlier today for some media 
>files,
> > seems this CVS version I got today already included the same fix I did 
>for
> > my 1.0 pre7 try2 code - dstride.y=64 instead of 16 since it's a 128 bit
> > memory I guess. Also the missing expand filter features for roundup and
> > aspect from pre7try2 found in CVS souce, so I didn't add my patch, they 
>are
> > almost identical, except I used double, it's float in CVS.
> > Do we have a patch ready to get rid of the menu OSD left on blank bands
> > added by expand filter?
> >
>
>I don't know of any patch for this.
>
>
> > --- nvidia_vid.c.org	2005-11-09 11:10:45.000000000 -0500
> > +++ nvidia_vid.c	2006-02-08 00:05:06.000000000 -0500
> > @@ -31,7 +31,7 @@
> >
> >
> > #define MAX_FRAMES 3
> > -#define NV04_BES_SIZE 1024*2000*4
> > +#define NV04_BES_SIZE 2048*2000*4
> >
>
>Why did you change this?

I was thinking the max 2D resolution for new cards changed to 2048x2000, 
just to give room for those modes. So this brings 4KB extra for nv10 and 
above.
>
>
> >
> > static vidix_capability_t nvidia_cap = {
> > @@ -144,6 +144,7 @@
> >    {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30},
> >    {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30},
> >    {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30},
> > +  {DEVICE_NVIDIA_NV34_GEFORCE_FX3,NV_ARCH_30},
> >    {DEVICE_NVIDIA_NV34M_GEFORCE_FX,NV_ARCH_30},
> >    {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30},
> >    {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30},
> > @@ -328,7 +329,11 @@
> > }
> >
>
>Ok.
>
> > static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){
> > -	return ((VID_RD32 (chip->PFB, 0x20C) >> 20) & 0x000000FF) * 1024 * 
>1024;
> > +	return VID_RD32 (chip->PFB, 0x20C) & 0x0FF00000;
> > +}
> > +
> > +static unsigned long rivatv_fbsize_nv30 (struct rivatv_chip *chip){
> > +	return VID_RD32 (chip->PFB, 0x20C) & 0x1FF00000;
> > }
> >
>
>Hm looks like X does something like
>VID_RD32(chip->PFB,0x20C) &0xFFF00000 so maybe this would work for all 
>cards
> >= nv10

Yes, it could be. Just not so sure if those bits above 1FF are used for 
other register. 3FF could be enough for now, haven't seen a 1G Video card 
yet.
>
>
> > //lock funcs
> > @@ -479,15 +484,13 @@
> > }
> >
> > static void nv_getscreenproperties(struct rivatv_info *info){
> > -  uint32_t bpp=0;
> > +  uint32_t bpp=0,x;
> >    info->chip.lock(&info->chip, 0);
> >    /*get screen depth*/
> >    VID_WR08(info->chip.PCIO, 0x03D4,0x28);
> >    bpp = VID_RD08(info->chip.PCIO,0x03D5)&0x3;
> > -  if(bpp==3)bpp=4;
> >    if((bpp == 2) && (VID_RD32(info->chip.PVIDEO,0x600) & 0x00001000) ==
> > 0x0)info->depth=15;
> > -  else info->depth = bpp*8;
> > -  info->bps=bpp;
> > +  else info->depth = 0x04 << bpp;
>
>Are you sure this is correct?
>Before bpp was either 2 or 4 so depth was 16 or 32
>With your patch it can be 24, too and as far as I remember at least the
>riva128 did not like this.

This will not give you 24, what this does is the exact same as 
if(bpp==3)bpp==4. It's 0x04<<bpp, will result in 8/16/32.

>
>Regards
>
>Sascha
>
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