[Mplayer-cvslog] CVS: main/drivers/radeon radeonfb.c,1.3,1.4 radeon.h,1.3,1.4

[Nick Kurshev]

Update of /cvsroot/mplayer/main/drivers/radeon
In directory mplayer:/var/tmp.root/cvs-serv1331/main/drivers/radeon

Modified Files:
	radeonfb.c radeon.h 
Log Message:
Merge with Ani Joshi's radeonfb-0.1.0

Index: radeonfb.c
===================================================================
RCS file: /cvsroot/mplayer/main/drivers/radeon/radeonfb.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -r1.3 -r1.4
--- radeonfb.c	18 Sep 2001 16:16:19 -0000	1.3
+++ radeonfb.c	18 Sep 2001 16:26:11 -0000	1.4
@@ -1,17 +1,19 @@
-/*
- *	drivers/video/radeonfb.c
- *	framebuffer driver for ATI Radeon chipset video boards
- *
- *	Copyright 2000	Ani Joshi <ajoshi at unixbox.com>
- *
- *
- *	ChangeLog:
- *	2000-08-03	initial version 0.0.1
- *	2000-09-10	more bug fixes, public release 0.0.5
- *	2001-02-19	mode bug fixes, 0.0.7
[...3930 lines suppressed...]
+	OUTREG(DST_WIDTH_HEIGHT, (width << 16) | height);
+}
+
+
+
+
+#ifdef FBCON_HAS_CFB8
+static struct display_switch fbcon_radeon8 = {
+	setup:			fbcon_cfb8_setup,
+	bmove:			fbcon_radeon_bmove,
+	clear:			fbcon_cfb8_clear,
+	putc:			fbcon_cfb8_putc,
+	putcs:			fbcon_cfb8_putcs,
+	revc:			fbcon_cfb8_revc,
+	clear_margins:		fbcon_cfb8_clear_margins,
+	fontwidthmask:		FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
+};
+#endif
+
+#endif /* 0 */

Index: radeon.h
===================================================================
RCS file: /cvsroot/mplayer/main/drivers/radeon/radeon.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -u -r1.3 -r1.4
--- radeon.h	18 Sep 2001 16:16:19 -0000	1.3
+++ radeon.h	18 Sep 2001 16:26:11 -0000	1.4
@@ -1,666 +1,673 @@
-#ifndef _RADEON_H
-#define _RADEON_H
-
-
-/* radeon PCI ids */
-#define PCI_DEVICE_ID_RADEON_QD		0x5144
-#define PCI_DEVICE_ID_RADEON_QE		0x5145
-#define PCI_DEVICE_ID_RADEON_QF		0x5146
-#define PCI_DEVICE_ID_RADEON_QG		0x5147
+#ifndef _RADEON_H
+#define _RADEON_H
[...1306 lines suppressed...]
+
+#define CONFIG_MEMSIZE_MASK		0x1f000000
+#define MEM_CFG_TYPE			0x40000000
+#define DST_OFFSET_MASK			0x003fffff
+#define DST_PITCH_MASK			0x3fc00000
+#define DEFAULT_TILE_MASK		0xc0000000
+#define	PPLL_DIV_SEL_MASK		0x00000300
+#define	PPLL_RESET			0x00000001
+#define PPLL_ATOMIC_UPDATE_EN		0x00010000
+#define PPLL_REF_DIV_MASK		0x000003ff
+#define	PPLL_FB3_DIV_MASK		0x000007ff
+#define	PPLL_POST3_DIV_MASK		0x00070000
+#define PPLL_ATOMIC_UPDATE_R		0x00008000
+#define PPLL_ATOMIC_UPDATE_W		0x00008000
+#define	PPLL_VGA_ATOMIC_UPDATE_EN	0x00020000
+
+#define GUI_ACTIVE			0x80000000
+
+#endif	/* _RADEON_H */
+