[FFmpeg-user] can swscale handle AV_PIX_FMT_YUV444P input/output?
Andrew Randrianasulu
randrianasulu at gmail.com
Fri Sep 6 16:02:16 EEST 2024
пт, 6 сент. 2024 г., 15:02 Andrew Randrianasulu <randrianasulu at gmail.com>:
> On Thu, Sep 5, 2024 at 9:21 AM Andrew Randrianasulu
> <randrianasulu at gmail.com> wrote:
> >
> > On Wed, Sep 4, 2024 at 11:27 PM Andrew Randrianasulu
> > <randrianasulu at gmail.com> wrote:
> > >
> > > https://www.cinelerra-gg.org/bugtracker/view.php?id=665
> > >
> > > we run into strange problem:
> > >
> > > if cinelerra-gg uses RGBA-8 format internally we can process yuv444p
> (full chroma) test sample made with
> > >
> > > ffmpeg -f lavfi -i yuvtestsrc -frames 1 -color_range 2
> /dev/shm/yuv-test.y4m
> > >
> > > by rendering it to y4m (yuv444p pixel format) and then comparing two
> files does not show big difference.
> > >
> > > Yet if we switch our pipeline to yuv (8 bit, 4:4:4) result is totally
> off (in YUVviewer) for same y4m render.
> > >
> > > I looked in libswscale and can't see much handling for specifically
> > >
> > > guest at slax:~/botva/src/mplayer/ffmpeg/libswscale$ grep
> "AV_PIX_FMT_YUV444P" *.c
> > > input.c: case AV_PIX_FMT_YUV444P9LE:
> > > input.c: case AV_PIX_FMT_YUV444P10LE:
> > > input.c: case AV_PIX_FMT_YUV444P12LE:
> > > input.c: case AV_PIX_FMT_YUV444P14LE:
> > > input.c: case AV_PIX_FMT_YUV444P16LE:
> > > input.c: case AV_PIX_FMT_YUV444P9BE:
> > > input.c: case AV_PIX_FMT_YUV444P10BE:
> > > input.c: case AV_PIX_FMT_YUV444P12BE:
> > > input.c: case AV_PIX_FMT_YUV444P14BE:
> > > input.c: case AV_PIX_FMT_YUV444P16BE:
> > > input.c: case AV_PIX_FMT_YUV444P9LE:
> > > input.c: case AV_PIX_FMT_YUV444P10LE:
> > > input.c: case AV_PIX_FMT_YUV444P12LE:
> > > input.c: case AV_PIX_FMT_YUV444P14LE:
> > > input.c: case AV_PIX_FMT_YUV444P16LE:
> > > input.c: case AV_PIX_FMT_YUV444P9BE:
> > > input.c: case AV_PIX_FMT_YUV444P10BE:
> > > input.c: case AV_PIX_FMT_YUV444P12BE:
> > > input.c: case AV_PIX_FMT_YUV444P14BE:
> > > input.c: case AV_PIX_FMT_YUV444P16BE:
> > > swscale_unscaled.c: if ((srcFormat == AV_PIX_FMT_YUV444P ||
> srcFormat == AV_PIX_FMT_YUVA444P) &&
> > > swscale_unscaled.c: if (dstFormat == AV_PIX_FMT_YUV444P &&
> > > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat,
> dstFormat, AV_PIX_FMT_YUV444P9) ||
> > > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat,
> dstFormat, AV_PIX_FMT_YUV444P10) ||
> > > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat,
> dstFormat, AV_PIX_FMT_YUV444P12) ||
> > > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat,
> dstFormat, AV_PIX_FMT_YUV444P14) ||
> > > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat,
> dstFormat, AV_PIX_FMT_YUV444P16))
> > > utils.c: [AV_PIX_FMT_YUV444P] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P16LE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P16BE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P9BE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P9LE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P10BE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P10LE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P12BE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P12LE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P14BE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P14LE] = { 1, 1 },
> > > utils.c: *format = AV_PIX_FMT_YUV444P;
> > > utils.c: case AV_PIX_FMT_YUVA444P: return
> AV_PIX_FMT_YUV444P;
> > > utils.c: case AV_PIX_FMT_YUVA444P9BE: return
> AV_PIX_FMT_YUV444P9;
> > > utils.c: case AV_PIX_FMT_YUVA444P9LE: return
> AV_PIX_FMT_YUV444P9;
> > > utils.c: case AV_PIX_FMT_YUVA444P10BE: return
> AV_PIX_FMT_YUV444P10;
> > > utils.c: case AV_PIX_FMT_YUVA444P10LE: return
> AV_PIX_FMT_YUV444P10;
> > > utils.c: case AV_PIX_FMT_YUVA444P16BE: return
> AV_PIX_FMT_YUV444P16;
> > > utils.c: case AV_PIX_FMT_YUVA444P16LE: return
> AV_PIX_FMT_YUV444P16;
> > >
> > > it seems input.c does not deal well with specifically this format?
> There is no default case in switches ...
> > >
> > > in swscale_unscaled I also mostly see specific yuv-nv12 wrappers, not
> yuv444 standalone.
> > >
> > > util.c is again declares what to do with >8 bpc yuv, mostly.
> > >
> > > did I miss something important?
> > >
> > > our ffmpeg mappings live at
> > >
> > >
> https://git.cinelerra-gg.org/git/?p=goodguy/cinelerra.git;a=blob;f=cinelerra-5.1/cinelerra/ffmpeg.C;h=9b8832dd718c94dd8b815edc7eb5c9d732953dd6;hb=HEAD
> > >
>
> so, it seems for our processing we should skip
> sws_setColorspaceDetails call if we have both input buffer as yuv and
> output pix_fmt is also yuv-something
>
> Is there any av_* function to see if pixfmt is yuv ? Our mappings
> obviously incomplete ....
>
ah, there is something in swscale_internal.h
static av_always_inline int isYUV(enum AVPixelFormat pix_fmt)
{
const
AVPixFmtDescriptor *desc = av_pix_fmt_desc_get(pix_fmt);
av_assert0(desc);
return !(desc->flags &
AV_PIX_FMT_FLAG_RGB) && desc->nb_components >= 2; }
looks simple enough to add to our code (gpl2)
>
> > > ps: non-ffmpeg png writer seems to output nearly exactly same png if I
> set cingg to yuv8 or rgba8 internal processing. So, for same input test
> file as long as libswscale did its job once on input - pipeline itself
> does not ruin video, as long as there was no second swscale ? unfortunately
> we do not have direct yuv writer, so at the end our yuv444 transformed into
> rgba for saving into tga or png or ppm by our routines.
> > >
> >
> > so, I used ffmpeg git up to d9f594209fb1a9c87017034f943dcb311a9d2896
> >
> > make testprog (after ./configure)
> >
> > then I ran
> >
> > guest at slax:/dev/shm/ffmpeg/libswscale/tests$ ./swscale -dst yuv444p >
> yuv444.log
> > cat yuv444.log | grep flags=524296 | grep "96x 96" >
> 96_yuv444p_flags524296.log
> >
> > from that I see only few conversions show errors > 1?
> >
> > cat 96_yuv444p_flags524296.log
> > yuv420p 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD= 0,
> > 0, 0, 0
> > yuyv422 96x96 -> yuv444p 96x 96 flags=524296 CRC=b060ca43 SSD= 0,
> > 4, 2, 0
> > rgb24 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,
> > 0, 0, 0
> > bgr24 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,
> > 0, 0, 0
> > yuv422p 96x96 -> yuv444p 96x 96 flags=524296 CRC=df1de98f SSD= 0,
> > 1, 0, 0
> > yuv444p 96x96 -> yuv444p 96x 96 flags=524296 CRC=5073aeb9 SSD= 0,
> > 1, 0, 0
> > yuv410p 96x96 -> yuv444p 96x 96 flags=524296 CRC=48e60437 SSD= 0,
> > 10, 9, 0
> > yuv411p 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb8ac6fb SSD= 0,
> > 4, 5, 0
> > gray 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD= 0,
> > 0, 0, 0
> > monow 96x96 -> yuv444p 96x 96 flags=524296 CRC=01e024ce SSD=14850,
> > 0, 0, 0
> > monob 96x96 -> yuv444p 96x 96 flags=524296 CRC=6b366fbe SSD=14769,
> > 0, 0, 0
> > yuvj420p 96x96 -> yuv444p 96x 96 flags=524296 CRC=f5fc89f5 SSD=
> > 0, 0, 0, 0
> > yuvj422p 96x96 -> yuv444p 96x 96 flags=524296 CRC=28bcb4f2 SSD=
> > 0, 0, 0, 0
> > yuvj444p 96x96 -> yuv444p 96x 96 flags=524296 CRC=eb23ece1 SSD=
> > 0, 1, 0, 0
> > uyvy422 96x96 -> yuv444p 96x 96 flags=524296 CRC=c7973100 SSD= 0,
> > 4, 2, 0
> > bgr8 96x96 -> yuv444p 96x 96 flags=524296 CRC=2be3ab32 SSD= 92,
> > 6, 3, 0
> > bgr4_byte 96x96 -> yuv444p 96x 96 flags=524296 CRC=a4f9f904 SSD=
> > 1256, 38, 33, 0
> > rgb8 96x96 -> yuv444p 96x 96 flags=524296 CRC=2be3ab32 SSD= 92,
> > 6, 3, 0
> > rgb4_byte 96x96 -> yuv444p 96x 96 flags=524296 CRC=a4f9f904 SSD=
> > 1256, 38, 33, 0
> > nv12 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD= 0,
> > 0, 0, 0
> > nv21 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD= 0,
> > 0, 0, 0
> > argb 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,
> > 0, 0, 0
> > rgba 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,
> > 0, 0, 0
> > abgr 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,
> > 0, 0, 0
> > bgra 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,
> > 0, 0, 0
> > gray16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=2e43f8fd SSD=
> > 0, 0, 0, 0
> > gray16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=2e43f8fd SSD=
> > 0, 0, 0, 0
> > yuv440p 96x96 -> yuv444p 96x 96 flags=524296 CRC=244073c9 SSD= 0,
> > 0, 0, 0
> > yuvj440p 96x96 -> yuv444p 96x 96 flags=524296 CRC=228c0b93 SSD=
> > 0, 0, 0, 0
> > yuva420p 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD=
> > 0, 0, 0, 0
> > rgb48be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,
> > 0, 0, 0
> > rgb48le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,
> > 0, 0, 0
> > rgb565be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c3d3be78 SSD=
> > 2, 4, 3, 0
> > rgb565le 96x96 -> yuv444p 96x 96 flags=524296 CRC=12edcd77 SSD=
> > 3, 0, 0, 0
> > rgb555be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9a8ede80 SSD=
> > 4, 4, 3, 0
> > rgb555le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da784ee1 SSD=
> > 4, 0, 0, 0
> > bgr565be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c3d3be78 SSD=
> > 2, 4, 3, 0
> > bgr565le 96x96 -> yuv444p 96x 96 flags=524296 CRC=0496c046 SSD=
> > 2, 0, 0, 0
> > bgr555be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9a8ede80 SSD=
> > 4, 4, 3, 0
> > bgr555le 96x96 -> yuv444p 96x 96 flags=524296 CRC=21eaab36 SSD=
> > 4, 0, 0, 0
> > yuv420p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv420p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv422p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv422p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv444p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=
> > 0, 1, 1, 0
> > yuv444p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=
> > 0, 1, 1, 0
> > rgb444le 96x96 -> yuv444p 96x 96 flags=524296 CRC=b651f543 SSD=
> > 28, 1, 1, 0
> > rgb444be 96x96 -> yuv444p 96x 96 flags=524296 CRC=eecdc127 SSD=
> > 11, 4, 3, 0
> > bgr444le 96x96 -> yuv444p 96x 96 flags=524296 CRC=b651f543 SSD=
> > 28, 1, 1, 0
> > bgr444be 96x96 -> yuv444p 96x 96 flags=524296 CRC=eecdc127 SSD=
> > 11, 4, 3, 0
> > ya8 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD= 0,
> > 0, 0, 0
> > bgr48be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,
> > 0, 0, 0
> > bgr48le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,
> > 0, 0, 0
> > yuv420p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv420p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv420p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv420p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv422p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv422p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv444p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=
> > 0, 1, 0, 0
> > yuv444p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=
> > 0, 1, 0, 0
> > yuv444p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=
> > 0, 1, 0, 0
> > yuv444p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=
> > 0, 1, 0, 0
> > yuv422p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=
> > 0, 0, 0, 0
> > yuv422p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=
> > 0, 0, 0, 0
> > gbrp 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,
> > 0, 0, 0
> > gbrp9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=333371d5 SSD= 0,
> > 1, 0, 0
> > gbrp9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=333371d5 SSD= 0,
> > 1, 0, 0
> > gbrp10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=
> > 0, 1, 0, 0
> > gbrp10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=
> > 0, 1, 0, 0
> > gbrp16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=
> > 0, 1, 0, 0
> > gbrp16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=
> > 0, 1, 0, 0
> > yuva422p 96x96 -> yuv444p 96x 96 flags=524296 CRC=df1de98f SSD=
> > 0, 1, 0, 0
> > yuva444p 96x96 -> yuv444p 96x 96 flags=524296 CRC=5073aeb9 SSD=
> > 0, 1, 0, 0
> > yuva420p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuva420p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuva422p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=
> > 0, 0, 0, 0
> > yuva422p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=
> > 0, 0, 0, 0
> > yuva444p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=
> > 0, 1, 0, 0
> > yuva444p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=
> > 0, 1, 0, 0
> > yuva420p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuva420p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuva422p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuva422p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuva444p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=
> > 0, 1, 0, 0
> > yuva444p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=
> > 0, 1, 0, 0
> > yuva420p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuva420p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuva422p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuva422p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuva444p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=
> > 0, 1, 1, 0
> > yuva444p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=
> > 0, 1, 1, 0
> > xyz12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=44ea94ba SSD= 1,
> > 0, 0, 0
> > xyz12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=44ea94ba SSD= 1,
> > 0, 0, 0
> > nv16 96x96 -> yuv444p 96x 96 flags=524296 CRC=df1de98f SSD= 0,
> > 1, 0, 0
> > rgba64be 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=
> > 0, 3, 2, 0
> > rgba64le 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=
> > 0, 3, 2, 0
> > bgra64be 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=
> > 0, 3, 2, 0
> > bgra64le 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=
> > 0, 3, 2, 0
> > yvyu422 96x96 -> yuv444p 96x 96 flags=524296 CRC=c7973100 SSD= 0,
> > 4, 2, 0
> > ya16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=5c8c4e0f SSD= 0,
> > 0, 0, 0
> > ya16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=5c8c4e0f SSD= 0,
> > 0, 0, 0
> > gbrap 96x96 -> yuv444p 96x 96 flags=524296 CRC=4d1e6edb SSD= 0,
> > 1, 0, 0
> > gbrap16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=
> > 0, 1, 0, 0
> > gbrap16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=
> > 0, 1, 0, 0
> > 0rgb 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,
> > 0, 0, 0
> > rgb0 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,
> > 0, 0, 0
> > 0bgr 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,
> > 0, 0, 0
> > bgr0 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,
> > 0, 0, 0
> > yuv420p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv420p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv420p14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv420p14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv422p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv422p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv422p14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv422p14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv444p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=
> > 0, 1, 0, 0
> > yuv444p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=
> > 0, 1, 0, 0
> > yuv444p14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=
> > 0, 1, 0, 0
> > yuv444p14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=
> > 0, 1, 0, 0
> > gbrp12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=
> > 0, 1, 0, 0
> > gbrp12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=
> > 0, 1, 0, 0
> > gbrp14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=
> > 0, 1, 0, 0
> > gbrp14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=
> > 0, 1, 0, 0
> > yuvj411p 96x96 -> yuv444p 96x 96 flags=524296 CRC=fc11b7a8 SSD=
> > 0, 4, 5, 0
> > yuv440p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=
> > 0, 0, 0, 0
> > yuv440p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=
> > 0, 0, 0, 0
> > yuv440p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=
> > 0, 0, 0, 0
> > yuv440p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=
> > 0, 0, 0, 0
> > ayuv64le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD=
> > 0, 1, 0, 0
> > p010le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e396057d SSD= 0,
> > 0, 0, 0
> > p010be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,
> > 0, 0, 0
> > gbrap12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=
> > 0, 1, 0, 0
> > gbrap12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=
> > 0, 1, 0, 0
> > gbrap10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=
> > 0, 1, 0, 0
> > gbrap10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=
> > 0, 1, 0, 0
> > gray12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=d9a892ec SSD=
> > 0, 958, 667, 0
> > gray12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=d9a892ec SSD=
> > 0, 958, 667, 0
> > gray10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=a29dc987 SSD=
> > 0, 958, 667, 0
> > gray10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=a29dc987 SSD=
> > 0, 958, 667, 0
> > p016le 96x96 -> yuv444p 96x 96 flags=524296 CRC=123d3ef9 SSD= 0,
> > 1, 0, 0
> > p016be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,
> > 0, 0, 0
> > gray9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=90e6a330 SSD= 0,
> > 958, 667, 0
> > gray9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=90e6a330 SSD= 0,
> > 958, 667, 0
> > gbrpf32be 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=
> > 0, 1, 0, 0
> > gbrpf32le 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=
> > 0, 1, 0, 0
> > gbrapf32be 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=
> > 0, 1, 0, 0
> > gbrapf32le 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=
> > 0, 1, 0, 0
> > gray14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=
> > 0, 958, 667, 0
> > gray14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=
> > 0, 958, 667, 0
> > grayf32be 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=
> > 0, 958, 667, 0
> > grayf32le 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=
> > 0, 958, 667, 0
> > yuva422p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuva422p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuva444p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=
> > 0, 1, 0, 0
> > yuva444p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=
> > 0, 1, 0, 0
> > nv24 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,
> > 1, 0, 0
> > nv42 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,
> > 1, 0, 0
> > y210le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > x2rgb10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=28220704 SSD=
> > 1, 3, 2, 0
> > x2bgr10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=28220704 SSD=
> > 1, 3, 2, 0
> > p210be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > p210le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > p410be 96x96 -> yuv444p 96x 96 flags=524296 CRC=15ee96d0 SSD= 0,
> > 1, 0, 0
> > p410le 96x96 -> yuv444p 96x 96 flags=524296 CRC=15ee96d0 SSD= 0,
> > 1, 0, 0
> > p216be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > p216le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > p416be 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,
> > 1, 0, 0
> > p416le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,
> > 1, 0, 0
> > vuya 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,
> > 1, 0, 0
> > vuyx 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,
> > 1, 0, 0
> > p012le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,
> > 0, 0, 0
> > p012be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,
> > 0, 0, 0
> > y212le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > xv30le 96x96 -> yuv444p 96x 96 flags=524296 CRC=15ee96d0 SSD= 0,
> > 1, 0, 0
> > xv36le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,
> > 1, 0, 0
> > p212be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > p212le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > p412be 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,
> > 1, 0, 0
> >
> >
> > p412le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,
> > 1, 0, 0
> > gbrap14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=
> > 0, 1, 0, 0
> > gbrap14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=
> > 0, 1, 0, 0
> >
> > =====
> >
> > grayf32le
> > gray12be
> > yvyu422
> > bgra64le
> > rgb444le
> > bgr555be
> > yuv410p
> > yuv411p
> > yuyv422
> >
> > This is on
> >
> > LANG=C lscpu
> > Architecture: x86_64
> > CPU op-mode(s): 32-bit, 64-bit
> > Address sizes: 48 bits physical, 48 bits virtual
> > Byte Order: Little Endian
> > CPU(s): 4
> > On-line CPU(s) list: 0-3
> > Vendor ID: AuthenticAMD
> > Model name: AMD FX(tm)-4300 Quad-Core Processor
> > CPU family: 21
> > Model: 2
> > Thread(s) per core: 2
> > Core(s) per socket: 2
> > Socket(s): 1
> > Stepping: 0
> > Frequency boost: enabled
> > CPU max MHz: 3800.0000
> > CPU min MHz: 1400.0000
> > BogoMIPS: 7583.64
> > Flags: fpu vme de pse tsc msr pae mce cx8 apic sep
> > mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht sys
> > call nx mmxext fxsr_opt pdpe1gb rdtscp lm
> > constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperf
> > mperf pni pclmulqdq monitor ssse3 fma cx16
> > sse4_1 sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy sv
> > m extapic cr8_legacy abm sse4a misalignsse
> > 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 tce nodeid_msr
> > tbm topoext perfctr_core perfctr_nb cpb
> > hw_pstate ssbd vmmcall bmi1 arat npt lbrv svm_lock nrip_save ts
> > c_scale vmcb_clean flushbyasid decodeassists
> > pausefilter pfthreshold
> >
> > on Slackware 15.0 i586 with 64-bit kernel.
>
пт, 6 сент. 2024 г., 15:02 Andrew Randrianasulu <randrianasulu at gmail.com>:
> On Thu, Sep 5, 2024 at 9:21 AM Andrew Randrianasulu
> <randrianasulu at gmail.com> wrote:
> >
> > On Wed, Sep 4, 2024 at 11:27 PM Andrew Randrianasulu
> > <randrianasulu at gmail.com> wrote:
> > >
> > > https://www.cinelerra-gg.org/bugtracker/view.php?id=665
> > >
> > > we run into strange problem:
> > >
> > > if cinelerra-gg uses RGBA-8 format internally we can process yuv444p
> (full chroma) test sample made with
> > >
> > > ffmpeg -f lavfi -i yuvtestsrc -frames 1 -color_range 2
> /dev/shm/yuv-test.y4m
> > >
> > > by rendering it to y4m (yuv444p pixel format) and then comparing two
> files does not show big difference.
> > >
> > > Yet if we switch our pipeline to yuv (8 bit, 4:4:4) result is totally
> off (in YUVviewer) for same y4m render.
> > >
> > > I looked in libswscale and can't see much handling for specifically
> > >
> > > guest at slax:~/botva/src/mplayer/ffmpeg/libswscale$ grep
> "AV_PIX_FMT_YUV444P" *.c
> > > input.c: case AV_PIX_FMT_YUV444P9LE:
> > > input.c: case AV_PIX_FMT_YUV444P10LE:
> > > input.c: case AV_PIX_FMT_YUV444P12LE:
> > > input.c: case AV_PIX_FMT_YUV444P14LE:
> > > input.c: case AV_PIX_FMT_YUV444P16LE:
> > > input.c: case AV_PIX_FMT_YUV444P9BE:
> > > input.c: case AV_PIX_FMT_YUV444P10BE:
> > > input.c: case AV_PIX_FMT_YUV444P12BE:
> > > input.c: case AV_PIX_FMT_YUV444P14BE:
> > > input.c: case AV_PIX_FMT_YUV444P16BE:
> > > input.c: case AV_PIX_FMT_YUV444P9LE:
> > > input.c: case AV_PIX_FMT_YUV444P10LE:
> > > input.c: case AV_PIX_FMT_YUV444P12LE:
> > > input.c: case AV_PIX_FMT_YUV444P14LE:
> > > input.c: case AV_PIX_FMT_YUV444P16LE:
> > > input.c: case AV_PIX_FMT_YUV444P9BE:
> > > input.c: case AV_PIX_FMT_YUV444P10BE:
> > > input.c: case AV_PIX_FMT_YUV444P12BE:
> > > input.c: case AV_PIX_FMT_YUV444P14BE:
> > > input.c: case AV_PIX_FMT_YUV444P16BE:
> > > swscale_unscaled.c: if ((srcFormat == AV_PIX_FMT_YUV444P ||
> srcFormat == AV_PIX_FMT_YUVA444P) &&
> > > swscale_unscaled.c: if (dstFormat == AV_PIX_FMT_YUV444P &&
> > > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat,
> dstFormat, AV_PIX_FMT_YUV444P9) ||
> > > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat,
> dstFormat, AV_PIX_FMT_YUV444P10) ||
> > > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat,
> dstFormat, AV_PIX_FMT_YUV444P12) ||
> > > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat,
> dstFormat, AV_PIX_FMT_YUV444P14) ||
> > > swscale_unscaled.c: IS_DIFFERENT_ENDIANESS(srcFormat,
> dstFormat, AV_PIX_FMT_YUV444P16))
> > > utils.c: [AV_PIX_FMT_YUV444P] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P16LE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P16BE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P9BE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P9LE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P10BE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P10LE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P12BE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P12LE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P14BE] = { 1, 1 },
> > > utils.c: [AV_PIX_FMT_YUV444P14LE] = { 1, 1 },
> > > utils.c: *format = AV_PIX_FMT_YUV444P;
> > > utils.c: case AV_PIX_FMT_YUVA444P: return
> AV_PIX_FMT_YUV444P;
> > > utils.c: case AV_PIX_FMT_YUVA444P9BE: return
> AV_PIX_FMT_YUV444P9;
> > > utils.c: case AV_PIX_FMT_YUVA444P9LE: return
> AV_PIX_FMT_YUV444P9;
> > > utils.c: case AV_PIX_FMT_YUVA444P10BE: return
> AV_PIX_FMT_YUV444P10;
> > > utils.c: case AV_PIX_FMT_YUVA444P10LE: return
> AV_PIX_FMT_YUV444P10;
> > > utils.c: case AV_PIX_FMT_YUVA444P16BE: return
> AV_PIX_FMT_YUV444P16;
> > > utils.c: case AV_PIX_FMT_YUVA444P16LE: return
> AV_PIX_FMT_YUV444P16;
> > >
> > > it seems input.c does not deal well with specifically this format?
> There is no default case in switches ...
> > >
> > > in swscale_unscaled I also mostly see specific yuv-nv12 wrappers, not
> yuv444 standalone.
> > >
> > > util.c is again declares what to do with >8 bpc yuv, mostly.
> > >
> > > did I miss something important?
> > >
> > > our ffmpeg mappings live at
> > >
> > >
> https://git.cinelerra-gg.org/git/?p=goodguy/cinelerra.git;a=blob;f=cinelerra-5.1/cinelerra/ffmpeg.C;h=9b8832dd718c94dd8b815edc7eb5c9d732953dd6;hb=HEAD
> > >
>
> so, it seems for our processing we should skip
> sws_setColorspaceDetails call if we have both input buffer as yuv and
> output pix_fmt is also yuv-something
>
> Is there any av_* function to see if pixfmt is yuv ? Our mappings
> obviously incomplete ....
>
>
> > > ps: non-ffmpeg png writer seems to output nearly exactly same png if I
> set cingg to yuv8 or rgba8 internal processing. So, for same input test
> file as long as libswscale did its job once on input - pipeline itself
> does not ruin video, as long as there was no second swscale ? unfortunately
> we do not have direct yuv writer, so at the end our yuv444 transformed into
> rgba for saving into tga or png or ppm by our routines.
> > >
> >
> > so, I used ffmpeg git up to d9f594209fb1a9c87017034f943dcb311a9d2896
> >
> > make testprog (after ./configure)
> >
> > then I ran
> >
> > guest at slax:/dev/shm/ffmpeg/libswscale/tests$ ./swscale -dst yuv444p >
> yuv444.log
> > cat yuv444.log | grep flags=524296 | grep "96x 96" >
> 96_yuv444p_flags524296.log
> >
> > from that I see only few conversions show errors > 1?
> >
> > cat 96_yuv444p_flags524296.log
> > yuv420p 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD= 0,
> > 0, 0, 0
> > yuyv422 96x96 -> yuv444p 96x 96 flags=524296 CRC=b060ca43 SSD= 0,
> > 4, 2, 0
> > rgb24 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,
> > 0, 0, 0
> > bgr24 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,
> > 0, 0, 0
> > yuv422p 96x96 -> yuv444p 96x 96 flags=524296 CRC=df1de98f SSD= 0,
> > 1, 0, 0
> > yuv444p 96x96 -> yuv444p 96x 96 flags=524296 CRC=5073aeb9 SSD= 0,
> > 1, 0, 0
> > yuv410p 96x96 -> yuv444p 96x 96 flags=524296 CRC=48e60437 SSD= 0,
> > 10, 9, 0
> > yuv411p 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb8ac6fb SSD= 0,
> > 4, 5, 0
> > gray 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD= 0,
> > 0, 0, 0
> > monow 96x96 -> yuv444p 96x 96 flags=524296 CRC=01e024ce SSD=14850,
> > 0, 0, 0
> > monob 96x96 -> yuv444p 96x 96 flags=524296 CRC=6b366fbe SSD=14769,
> > 0, 0, 0
> > yuvj420p 96x96 -> yuv444p 96x 96 flags=524296 CRC=f5fc89f5 SSD=
> > 0, 0, 0, 0
> > yuvj422p 96x96 -> yuv444p 96x 96 flags=524296 CRC=28bcb4f2 SSD=
> > 0, 0, 0, 0
> > yuvj444p 96x96 -> yuv444p 96x 96 flags=524296 CRC=eb23ece1 SSD=
> > 0, 1, 0, 0
> > uyvy422 96x96 -> yuv444p 96x 96 flags=524296 CRC=c7973100 SSD= 0,
> > 4, 2, 0
> > bgr8 96x96 -> yuv444p 96x 96 flags=524296 CRC=2be3ab32 SSD= 92,
> > 6, 3, 0
> > bgr4_byte 96x96 -> yuv444p 96x 96 flags=524296 CRC=a4f9f904 SSD=
> > 1256, 38, 33, 0
> > rgb8 96x96 -> yuv444p 96x 96 flags=524296 CRC=2be3ab32 SSD= 92,
> > 6, 3, 0
> > rgb4_byte 96x96 -> yuv444p 96x 96 flags=524296 CRC=a4f9f904 SSD=
> > 1256, 38, 33, 0
> > nv12 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD= 0,
> > 0, 0, 0
> > nv21 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD= 0,
> > 0, 0, 0
> > argb 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,
> > 0, 0, 0
> > rgba 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,
> > 0, 0, 0
> > abgr 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,
> > 0, 0, 0
> > bgra 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,
> > 0, 0, 0
> > gray16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=2e43f8fd SSD=
> > 0, 0, 0, 0
> > gray16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=2e43f8fd SSD=
> > 0, 0, 0, 0
> > yuv440p 96x96 -> yuv444p 96x 96 flags=524296 CRC=244073c9 SSD= 0,
> > 0, 0, 0
> > yuvj440p 96x96 -> yuv444p 96x 96 flags=524296 CRC=228c0b93 SSD=
> > 0, 0, 0, 0
> > yuva420p 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb289408 SSD=
> > 0, 0, 0, 0
> > rgb48be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,
> > 0, 0, 0
> > rgb48le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,
> > 0, 0, 0
> > rgb565be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c3d3be78 SSD=
> > 2, 4, 3, 0
> > rgb565le 96x96 -> yuv444p 96x 96 flags=524296 CRC=12edcd77 SSD=
> > 3, 0, 0, 0
> > rgb555be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9a8ede80 SSD=
> > 4, 4, 3, 0
> > rgb555le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da784ee1 SSD=
> > 4, 0, 0, 0
> > bgr565be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c3d3be78 SSD=
> > 2, 4, 3, 0
> > bgr565le 96x96 -> yuv444p 96x 96 flags=524296 CRC=0496c046 SSD=
> > 2, 0, 0, 0
> > bgr555be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9a8ede80 SSD=
> > 4, 4, 3, 0
> > bgr555le 96x96 -> yuv444p 96x 96 flags=524296 CRC=21eaab36 SSD=
> > 4, 0, 0, 0
> > yuv420p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv420p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv422p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv422p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv444p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=
> > 0, 1, 1, 0
> > yuv444p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=
> > 0, 1, 1, 0
> > rgb444le 96x96 -> yuv444p 96x 96 flags=524296 CRC=b651f543 SSD=
> > 28, 1, 1, 0
> > rgb444be 96x96 -> yuv444p 96x 96 flags=524296 CRC=eecdc127 SSD=
> > 11, 4, 3, 0
> > bgr444le 96x96 -> yuv444p 96x 96 flags=524296 CRC=b651f543 SSD=
> > 28, 1, 1, 0
> > bgr444be 96x96 -> yuv444p 96x 96 flags=524296 CRC=eecdc127 SSD=
> > 11, 4, 3, 0
> > ya8 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD= 0,
> > 0, 0, 0
> > bgr48be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,
> > 0, 0, 0
> > bgr48le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c37b68c4 SSD= 0,
> > 0, 0, 0
> > yuv420p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv420p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv420p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv420p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv422p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv422p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv444p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=
> > 0, 1, 0, 0
> > yuv444p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=
> > 0, 1, 0, 0
> > yuv444p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=
> > 0, 1, 0, 0
> > yuv444p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=
> > 0, 1, 0, 0
> > yuv422p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=
> > 0, 0, 0, 0
> > yuv422p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=
> > 0, 0, 0, 0
> > gbrp 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,
> > 0, 0, 0
> > gbrp9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=333371d5 SSD= 0,
> > 1, 0, 0
> > gbrp9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=333371d5 SSD= 0,
> > 1, 0, 0
> > gbrp10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=
> > 0, 1, 0, 0
> > gbrp10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=
> > 0, 1, 0, 0
> > gbrp16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=
> > 0, 1, 0, 0
> > gbrp16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=
> > 0, 1, 0, 0
> > yuva422p 96x96 -> yuv444p 96x 96 flags=524296 CRC=df1de98f SSD=
> > 0, 1, 0, 0
> > yuva444p 96x96 -> yuv444p 96x 96 flags=524296 CRC=5073aeb9 SSD=
> > 0, 1, 0, 0
> > yuva420p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuva420p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuva422p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=
> > 0, 0, 0, 0
> > yuva422p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=ed1a0423 SSD=
> > 0, 0, 0, 0
> > yuva444p9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=
> > 0, 1, 0, 0
> > yuva444p9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=06d4fc8a SSD=
> > 0, 1, 0, 0
> > yuva420p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuva420p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuva422p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuva422p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuva444p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=
> > 0, 1, 0, 0
> > yuva444p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=6688a6fc SSD=
> > 0, 1, 0, 0
> > yuva420p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuva420p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuva422p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuva422p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuva444p16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=
> > 0, 1, 1, 0
> > yuva444p16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=70250d37 SSD=
> > 0, 1, 1, 0
> > xyz12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=44ea94ba SSD= 1,
> > 0, 0, 0
> > xyz12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=44ea94ba SSD= 1,
> > 0, 0, 0
> > nv16 96x96 -> yuv444p 96x 96 flags=524296 CRC=df1de98f SSD= 0,
> > 1, 0, 0
> > rgba64be 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=
> > 0, 3, 2, 0
> > rgba64le 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=
> > 0, 3, 2, 0
> > bgra64be 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=
> > 0, 3, 2, 0
> > bgra64le 96x96 -> yuv444p 96x 96 flags=524296 CRC=3634df68 SSD=
> > 0, 3, 2, 0
> > yvyu422 96x96 -> yuv444p 96x 96 flags=524296 CRC=c7973100 SSD= 0,
> > 4, 2, 0
> > ya16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=5c8c4e0f SSD= 0,
> > 0, 0, 0
> > ya16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=5c8c4e0f SSD= 0,
> > 0, 0, 0
> > gbrap 96x96 -> yuv444p 96x 96 flags=524296 CRC=4d1e6edb SSD= 0,
> > 1, 0, 0
> > gbrap16be 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=
> > 0, 1, 0, 0
> > gbrap16le 96x96 -> yuv444p 96x 96 flags=524296 CRC=67885410 SSD=
> > 0, 1, 0, 0
> > 0rgb 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,
> > 0, 0, 0
> > rgb0 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,
> > 0, 0, 0
> > 0bgr 96x96 -> yuv444p 96x 96 flags=524296 CRC=4b24df28 SSD= 1,
> > 0, 0, 0
> > bgr0 96x96 -> yuv444p 96x 96 flags=524296 CRC=ef694d3f SSD= 1,
> > 0, 0, 0
> > yuv420p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv420p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv420p14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv420p14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD=
> > 0, 0, 0, 0
> > yuv422p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv422p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv422p14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv422p14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuv444p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=
> > 0, 1, 0, 0
> > yuv444p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=
> > 0, 1, 0, 0
> > yuv444p14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=
> > 0, 1, 0, 0
> > yuv444p14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=
> > 0, 1, 0, 0
> > gbrp12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=
> > 0, 1, 0, 0
> > gbrp12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=
> > 0, 1, 0, 0
> > gbrp14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=
> > 0, 1, 0, 0
> > gbrp14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=
> > 0, 1, 0, 0
> > yuvj411p 96x96 -> yuv444p 96x 96 flags=524296 CRC=fc11b7a8 SSD=
> > 0, 4, 5, 0
> > yuv440p10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=
> > 0, 0, 0, 0
> > yuv440p10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=
> > 0, 0, 0, 0
> > yuv440p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=
> > 0, 0, 0, 0
> > yuv440p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=d747b176 SSD=
> > 0, 0, 0, 0
> > ayuv64le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD=
> > 0, 1, 0, 0
> > p010le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e396057d SSD= 0,
> > 0, 0, 0
> > p010be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,
> > 0, 0, 0
> > gbrap12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=
> > 0, 1, 0, 0
> > gbrap12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=f6339681 SSD=
> > 0, 1, 0, 0
> > gbrap10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=
> > 0, 1, 0, 0
> > gbrap10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7a4edd98 SSD=
> > 0, 1, 0, 0
> > gray12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=d9a892ec SSD=
> > 0, 958, 667, 0
> > gray12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=d9a892ec SSD=
> > 0, 958, 667, 0
> > gray10be 96x96 -> yuv444p 96x 96 flags=524296 CRC=a29dc987 SSD=
> > 0, 958, 667, 0
> > gray10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=a29dc987 SSD=
> > 0, 958, 667, 0
> > p016le 96x96 -> yuv444p 96x 96 flags=524296 CRC=123d3ef9 SSD= 0,
> > 1, 0, 0
> > p016be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,
> > 0, 0, 0
> > gray9be 96x96 -> yuv444p 96x 96 flags=524296 CRC=90e6a330 SSD= 0,
> > 958, 667, 0
> > gray9le 96x96 -> yuv444p 96x 96 flags=524296 CRC=90e6a330 SSD= 0,
> > 958, 667, 0
> > gbrpf32be 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=
> > 0, 1, 0, 0
> > gbrpf32le 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=
> > 0, 1, 0, 0
> > gbrapf32be 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=
> > 0, 1, 0, 0
> > gbrapf32le 96x96 -> yuv444p 96x 96 flags=524296 CRC=5d960cda SSD=
> > 0, 1, 0, 0
> > gray14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=
> > 0, 958, 667, 0
> > gray14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=
> > 0, 958, 667, 0
> > grayf32be 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=
> > 0, 958, 667, 0
> > grayf32le 96x96 -> yuv444p 96x 96 flags=524296 CRC=cb24db3c SSD=
> > 0, 958, 667, 0
> > yuva422p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuva422p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD=
> > 0, 0, 0, 0
> > yuva444p12be 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=
> > 0, 1, 0, 0
> > yuva444p12le 96x96 -> yuv444p 96x 96 flags=524296 CRC=9ab9bff4 SSD=
> > 0, 1, 0, 0
> > nv24 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,
> > 1, 0, 0
> > nv42 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,
> > 1, 0, 0
> > y210le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > x2rgb10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=28220704 SSD=
> > 1, 3, 2, 0
> > x2bgr10le 96x96 -> yuv444p 96x 96 flags=524296 CRC=28220704 SSD=
> > 1, 3, 2, 0
> > p210be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > p210le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > p410be 96x96 -> yuv444p 96x 96 flags=524296 CRC=15ee96d0 SSD= 0,
> > 1, 0, 0
> > p410le 96x96 -> yuv444p 96x 96 flags=524296 CRC=15ee96d0 SSD= 0,
> > 1, 0, 0
> > p216be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > p216le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > p416be 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,
> > 1, 0, 0
> > p416le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,
> > 1, 0, 0
> > vuya 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,
> > 1, 0, 0
> > vuyx 96x96 -> yuv444p 96x 96 flags=524296 CRC=a28471c9 SSD= 0,
> > 1, 0, 0
> > p012le 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,
> > 0, 0, 0
> > p012be 96x96 -> yuv444p 96x 96 flags=524296 CRC=da579789 SSD= 0,
> > 0, 0, 0
> > y212le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > xv30le 96x96 -> yuv444p 96x 96 flags=524296 CRC=15ee96d0 SSD= 0,
> > 1, 0, 0
> > xv36le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,
> > 1, 0, 0
> > p212be 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > p212le 96x96 -> yuv444p 96x 96 flags=524296 CRC=c9b7464b SSD= 0,
> > 0, 0, 0
> > p412be 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,
> > 1, 0, 0
> >
> >
> > p412le 96x96 -> yuv444p 96x 96 flags=524296 CRC=e9ea9f55 SSD= 0,
> > 1, 0, 0
> > gbrap14be 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=
> > 0, 1, 0, 0
> > gbrap14le 96x96 -> yuv444p 96x 96 flags=524296 CRC=7cd163c7 SSD=
> > 0, 1, 0, 0
> >
> > =====
> >
> > grayf32le
> > gray12be
> > yvyu422
> > bgra64le
> > rgb444le
> > bgr555be
> > yuv410p
> > yuv411p
> > yuyv422
> >
> > This is on
> >
> > LANG=C lscpu
> > Architecture: x86_64
> > CPU op-mode(s): 32-bit, 64-bit
> > Address sizes: 48 bits physical, 48 bits virtual
> > Byte Order: Little Endian
> > CPU(s): 4
> > On-line CPU(s) list: 0-3
> > Vendor ID: AuthenticAMD
> > Model name: AMD FX(tm)-4300 Quad-Core Processor
> > CPU family: 21
> > Model: 2
> > Thread(s) per core: 2
> > Core(s) per socket: 2
> > Socket(s): 1
> > Stepping: 0
> > Frequency boost: enabled
> > CPU max MHz: 3800.0000
> > CPU min MHz: 1400.0000
> > BogoMIPS: 7583.64
> > Flags: fpu vme de pse tsc msr pae mce cx8 apic sep
> > mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ht sys
> > call nx mmxext fxsr_opt pdpe1gb rdtscp lm
> > constant_tsc rep_good nopl nonstop_tsc cpuid extd_apicid aperf
> > mperf pni pclmulqdq monitor ssse3 fma cx16
> > sse4_1 sse4_2 popcnt aes xsave avx f16c lahf_lm cmp_legacy sv
> > m extapic cr8_legacy abm sse4a misalignsse
> > 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 tce nodeid_msr
> > tbm topoext perfctr_core perfctr_nb cpb
> > hw_pstate ssbd vmmcall bmi1 arat npt lbrv svm_lock nrip_save ts
> > c_scale vmcb_clean flushbyasid decodeassists
> > pausefilter pfthreshold
> >
> > on Slackware 15.0 i586 with 64-bit kernel.
>
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