[FFmpeg-cvslog] lavc/vc1dsp: match C block layout in inv_trans_4x4_rvv

[Rémi Denis-Courmont]

ffmpeg | branch: master | Rémi Denis-Courmont <remi at remlab.net> | Mon Jun 10 20:29:56 2024 +0300| [6c05069e680f6b9055ac14bc19c663914b554fdb] | committer: Rémi Denis-Courmont

lavc/vc1dsp: match C block layout in inv_trans_4x4_rvv

Although checkasm does not verify this, the decoder requires that the
transform updates the input block exactly like the C code does.

This fixes vc1-ism, vc1_ilaced_twomv, vc1_sa00040, vc1_sa10091,
vc1_sa10143, vc1_sa20021, vc1test_smm0005 and wmv3-drm-dec tests.

> http://git.videolan.org/gitweb.cgi/ffmpeg.git/?a=commit;h=6c05069e680f6b9055ac14bc19c663914b554fdb
---

 libavcodec/riscv/vc1dsp_rvv.S | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/libavcodec/riscv/vc1dsp_rvv.S b/libavcodec/riscv/vc1dsp_rvv.S
index ab10027ae5..c4517d54f5 100644
--- a/libavcodec/riscv/vc1dsp_rvv.S
+++ b/libavcodec/riscv/vc1dsp_rvv.S
@@ -380,12 +380,12 @@ func ff_vc1_inv_trans_4x4_rvv, zve32x
         vlsseg4e16.v v0, (a2), a3
         li           t1, 3
         jal          t0, ff_vc1_inv_trans_4_rvv
-        vsseg4e16.v  v0, (a2)
-        addi         t1, a2, 1 * 4 * 2
+        vssseg4e16.v v0, (a2), a3
+        addi         t1, a2, 2 * 4 * 2
         vle16.v      v0, (a2)
-        addi         t2, a2, 2 * 4 * 2
+        addi         t2, a2, 4 * 4 * 2
         vle16.v      v1, (t1)
-        addi         t3, a2, 3 * 4 * 2
+        addi         t3, a2, 6 * 4 * 2
         vle16.v      v2, (t2)
         vle16.v      v3, (t3)
         li           t1, 7