[FFmpeg-cvslog] lavu/floatdsp: RISC-V V vector_fmul

Rémi Denis-Courmont git at videolan.org
Tue Sep 27 14:59:00 EEST 2022


ffmpeg | branch: master | Rémi Denis-Courmont <remi at remlab.net> | Mon Sep 26 17:52:30 2022 +0300| [7058af9969b737adbb1cd302cf8fa5feb7bc9e2b] | committer: Lynne

lavu/floatdsp: RISC-V V vector_fmul

> http://git.videolan.org/gitweb.cgi/ffmpeg.git/?a=commit;h=7058af9969b737adbb1cd302cf8fa5feb7bc9e2b
---

 libavutil/riscv/float_dsp_init.c |  6 +++++-
 libavutil/riscv/float_dsp_rvv.S  | 17 +++++++++++++++++
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/libavutil/riscv/float_dsp_init.c b/libavutil/riscv/float_dsp_init.c
index 3386139d49..2482094ab4 100644
--- a/libavutil/riscv/float_dsp_init.c
+++ b/libavutil/riscv/float_dsp_init.c
@@ -25,6 +25,8 @@
 #include "libavutil/cpu.h"
 #include "libavutil/float_dsp.h"
 
+void ff_vector_fmul_rvv(float *dst, const float *src0, const float *src1,
+                         int len);
 void ff_vector_fmul_scalar_rvv(float *dst, const float *src, float mul,
                                 int len);
 
@@ -36,8 +38,10 @@ av_cold void ff_float_dsp_init_riscv(AVFloatDSPContext *fdsp)
 #if HAVE_RVV
     int flags = av_get_cpu_flags();
 
-    if (flags & AV_CPU_FLAG_RVV_F32)
+    if (flags & AV_CPU_FLAG_RVV_F32) {
+        fdsp->vector_fmul = ff_vector_fmul_rvv;
         fdsp->vector_fmul_scalar = ff_vector_fmul_scalar_rvv;
+    }
 
     if (flags & AV_CPU_FLAG_RVV_F64)
         fdsp->vector_dmul_scalar = ff_vector_dmul_scalar_rvv;
diff --git a/libavutil/riscv/float_dsp_rvv.S b/libavutil/riscv/float_dsp_rvv.S
index 17dda471b4..00fb7354bb 100644
--- a/libavutil/riscv/float_dsp_rvv.S
+++ b/libavutil/riscv/float_dsp_rvv.S
@@ -21,6 +21,23 @@
 #include "config.h"
 #include "asm.S"
 
+// (a0) = (a1) * (a2) [0..a3-1]
+func ff_vector_fmul_rvv, zve32f
+1:
+        vsetvli  t0, a3, e32, m1, ta, ma
+        vle32.v  v16, (a1)
+        sub      a3, a3, t0
+        vle32.v  v24, (a2)
+        sh2add   a1, t0, a1
+        vfmul.vv v16, v16, v24
+        sh2add   a2, t0, a2
+        vse32.v  v16, (a0)
+        sh2add   a0, t0, a0
+        bnez     a3, 1b
+
+        ret
+endfunc
+
 // (a0) = (a1) * fa0 [0..a2-1]
 func ff_vector_fmul_scalar_rvv, zve32f
 NOHWF   fmv.w.x  fa0, a2



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