[FFmpeg-cvslog] ARM: rv34: fix asm syntax in dc transform functions

[Mans Rullgard]

ffmpeg | branch: master | Mans Rullgard <mans at mansr.com> | Thu Jan 12 19:37:31 2012 +0000| [81dc6a2a3cefc1f1bbbc249052b3374e524d1ea0] | committer: Janne Grunau

ARM: rv34: fix asm syntax in dc transform functions

Signed-off-by: Mans Rullgard <mans at mansr.com>
Signed-off-by: Janne Grunau <janne-libav at jannau.net>

> http://git.videolan.org/gitweb.cgi/ffmpeg.git/?a=commit;h=81dc6a2a3cefc1f1bbbc249052b3374e524d1ea0
---

 libavcodec/arm/rv34dsp_neon.S |   22 +++++++++++-----------
 1 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/libavcodec/arm/rv34dsp_neon.S b/libavcodec/arm/rv34dsp_neon.S
index e776af0..1e8d4b4 100644
--- a/libavcodec/arm/rv34dsp_neon.S
+++ b/libavcodec/arm/rv34dsp_neon.S
@@ -110,29 +110,29 @@ endfunc
 
 /* void rv34_inv_transform_dc_c(DCTELEM *block) */
 function ff_rv34_inv_transform_dc_neon, export=1
-        vld1.16         d28[], [r0:16]         @ block[0]
+        vld1.16         {d28[]}, [r0,:16]       @ block[0]
         vmov.i16        d4,  #169
         mov             r1,  #16
         vmull.s16       q3,  d28, d4
         vrshrn.s32      d0,  q3,  #10
-        vst1.16         {d0}, [r0:64], r1
-        vst1.16         {d0}, [r0:64], r1
-        vst1.16         {d0}, [r0:64], r1
-        vst1.16         {d0}, [r0:64], r1
+        vst1.16         {d0}, [r0,:64], r1
+        vst1.16         {d0}, [r0,:64], r1
+        vst1.16         {d0}, [r0,:64], r1
+        vst1.16         {d0}, [r0,:64], r1
         bx              lr
 endfunc
 
 /* void rv34_inv_transform_dc_noround_c(DCTELEM *block) */
 function ff_rv34_inv_transform_noround_dc_neon, export=1
-        vld1.16         d28[], [r0:16]         @ block[0]
+        vld1.16         {d28[]}, [r0,:16]       @ block[0]
         vmov.i16        d4,  #251
-        vorr.s16        d4,  #256              @ 13^2 * 3
+        vorr.s16        d4,  #256               @ 13^2 * 3
         mov             r1,  #16
         vmull.s16       q3,  d28, d4
         vshrn.s32       d0,  q3,  #11
-        vst1.64         {d0}, [r0:64], r1
-        vst1.64         {d0}, [r0:64], r1
-        vst1.64         {d0}, [r0:64], r1
-        vst1.64         {d0}, [r0:64], r1
+        vst1.64         {d0}, [r0,:64], r1
+        vst1.64         {d0}, [r0,:64], r1
+        vst1.64         {d0}, [r0,:64], r1
+        vst1.64         {d0}, [r0,:64], r1
         bx              lr
 endfunc